60 	if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)  in mtk_get_regmap()
68 	return ((pin >> 4) & pctl->devdata->port_mask)  in mtk_get_port()
69 			<< pctl->devdata->port_shf;  in mtk_get_port()
80 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;  in mtk_pmx_gpio_set_direction()
99 	reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;  in mtk_gpio_set()
122 	if (pctl->devdata->spec_ies_smt_set) {  in mtk_pconf_set_ies_smt()
123 		ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),  in mtk_pconf_set_ies_smt()
124 			pin, pctl->devdata->port_align, value);  in mtk_pconf_set_ies_smt()
132 		offset = pctl->devdata->ies_offset;  in mtk_pconf_set_ies_smt()
134 		offset = pctl->devdata->smt_offset;  in mtk_pconf_set_ies_smt()
148 	for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {  in mtk_find_pin_drv_grp_by_pin()
150 				pctl->devdata->pin_drv_grp + i;  in mtk_find_pin_drv_grp_by_pin()
166 	if (pin >= pctl->devdata->npins)  in mtk_pconf_set_driving()
170 	if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)  in mtk_pconf_set_driving()
173 	drv_grp = pctl->devdata->grp_desc + pin_drv->grp;  in mtk_pconf_set_driving()
200 	if (pctl->devdata->spec_pull_set) {  in mtk_pconf_set_pull_select()
201 		ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),  in mtk_pconf_set_pull_select()
202 			pin, pctl->devdata->port_align, isup, arg);  in mtk_pconf_set_pull_select()
217 			pctl->devdata->pullen_offset, pctl);  in mtk_pconf_set_pull_select()
220 			pctl->devdata->pullen_offset, pctl);  in mtk_pconf_set_pull_select()
224 			pctl->devdata->pullsel_offset, pctl);  in mtk_pconf_set_pull_select()
227 			pctl->devdata->pullsel_offset, pctl);  in mtk_pconf_set_pull_select()
322 	const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;  in mtk_pctrl_find_function_by_pin()
339 	for (i = 0; i < pctl->devdata->npins; i++) {  in mtk_pctrl_is_function_valid()
340 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;  in mtk_pctrl_is_function_valid()
441 		if (pin >= pctl->devdata->npins ||  in mtk_pctrl_dt_subnode_to_map()
569 	reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)  in mtk_pmx_set_mode()
570 			+ pctl->devdata->pinmux_offset;  in mtk_pmx_set_mode()
585 	for (i = 0; i < pctl->devdata->npins; i++) {  in mtk_find_pin_by_eint_num()
586 		pin = pctl->devdata->pins + i;  in mtk_find_pin_by_eint_num()
656 	reg_addr =  mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;  in mtk_gpio_get_direction()
671 			pctl->devdata->dout_offset;  in mtk_gpio_get()
674 			pctl->devdata->din_offset;  in mtk_gpio_get()
687 	pin = pctl->devdata->pins + offset;  in mtk_gpio_to_irq()
745 	if (eint_num >= pctl->devdata->ap_num)  in mtk_eint_get_offset()
746 		eint_base = pctl->devdata->ap_num;  in mtk_eint_get_offset()
763 		&pctl->devdata->eint_offsets;  in mtk_eint_can_en_debounce()
773 	if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))  in mtk_eint_can_en_debounce()
788 		&pctl->devdata->eint_offsets;  in mtk_eint_get_mask()
800 	const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);  in mtk_eint_flip_edge()
826 			&pctl->devdata->eint_offsets;  in mtk_eint_mask()
838 		&pctl->devdata->eint_offsets;  in mtk_eint_unmask()
860 	pin = pctl->devdata->pins + offset;  in mtk_gpio_set_debounce()
869 	set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;  in mtk_gpio_set_debounce()
870 	clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;  in mtk_gpio_set_debounce()
924 		&pctl->devdata->eint_offsets;  in mtk_eint_set_type()
970 		&pctl->devdata->eint_offsets;  in mtk_eint_ack()
991 		&pctl->devdata->eint_offsets;  in mtk_eint_init()
995 	for (i = 0; i < pctl->devdata->ap_num; i += 32) {  in mtk_eint_init()
1008 		&pctl->devdata->eint_offsets;  in mtk_eint_debounce_process()
1027 		&pctl->devdata->eint_offsets;  in mtk_eint_irq_handler()
1034 	     eint_num < pctl->devdata->ap_num;  in mtk_eint_irq_handler()
1068 			if (index < pctl->devdata->db_cnt)  in mtk_eint_irq_handler()
1080 	pctl->ngroups = pctl->devdata->npins;  in mtk_pctrl_build_state()
1094 	for (i = 0; i < pctl->devdata->npins; i++) {  in mtk_pctrl_build_state()
1095 		const struct mtk_desc_pin *pin = pctl->devdata->pins + i;  in mtk_pctrl_build_state()
1150 	pctl->devdata = data;  in mtk_pctrl_init()
1157 	pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),  in mtk_pctrl_init()
1162 	for (i = 0; i < pctl->devdata->npins; i++)  in mtk_pctrl_init()
1163 		pins[i] = pctl->devdata->pins[i].pin;  in mtk_pctrl_init()
1167 	mtk_pctrl_desc.npins = pctl->devdata->npins;  in mtk_pctrl_init()
1182 	pctl->chip->ngpio = pctl->devdata->npins;  in mtk_pctrl_init()
1195 			0, 0, pctl->devdata->npins);  in mtk_pctrl_init()
1215 	pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,  in mtk_pctrl_init()
1230 		pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);  in mtk_pctrl_init()
1238 	for (i = 0; i < pctl->devdata->ap_num; i++) {  in mtk_pctrl_init()