Lines Matching refs:padcfg0
70 u32 padcfg0; member
344 void __iomem *padcfg0; in intel_pinmux_set_mux() local
347 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0); in intel_pinmux_set_mux()
348 value = readl(padcfg0); in intel_pinmux_set_mux()
353 writel(value, padcfg0); in intel_pinmux_set_mux()
366 void __iomem *padcfg0; in intel_gpio_request_enable() local
377 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); in intel_gpio_request_enable()
379 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK; in intel_gpio_request_enable()
386 writel(value, padcfg0); in intel_gpio_request_enable()
398 void __iomem *padcfg0; in intel_gpio_set_direction() local
404 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); in intel_gpio_set_direction()
406 value = readl(padcfg0); in intel_gpio_set_direction()
411 writel(value, padcfg0); in intel_gpio_set_direction()
630 u32 padcfg0; in intel_gpio_set() local
633 padcfg0 = readl(reg); in intel_gpio_set()
635 padcfg0 |= PADCFG0_GPIOTXSTATE; in intel_gpio_set()
637 padcfg0 &= ~PADCFG0_GPIOTXSTATE; in intel_gpio_set()
638 writel(padcfg0, reg); in intel_gpio_set()
1070 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE; in intel_pinctrl_suspend()
1112 if (val != pads[i].padcfg0) { in intel_pinctrl_resume()
1113 writel(pads[i].padcfg0, padcfg); in intel_pinctrl_resume()