720 	u32 ctrl0, ctrl1;  in chv_pin_dbg_show()  local
725 	ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));  in chv_pin_dbg_show()
731 	if (ctrl0 & CHV_PADCTRL0_GPIOEN) {  in chv_pin_dbg_show()
736 		mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;  in chv_pin_dbg_show()
742 	seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1);  in chv_pin_dbg_show()
932 	u32 ctrl0;  in chv_gpio_set_direction()  local
936 	ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;  in chv_gpio_set_direction()
938 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;  in chv_gpio_set_direction()
940 		ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;  in chv_gpio_set_direction()
941 	chv_writel(ctrl0, reg);  in chv_gpio_set_direction()
964 	u32 ctrl0, ctrl1;  in chv_config_get()  local
969 	ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));  in chv_config_get()
973 	term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;  in chv_config_get()
982 		if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))  in chv_config_get()
1000 		if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))  in chv_config_get()
1022 		cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;  in chv_config_get()
1043 	u32 ctrl0, pull;  in chv_config_set_pull()  local
1046 	ctrl0 = readl(reg);  in chv_config_set_pull()
1050 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);  in chv_config_set_pull()
1054 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);  in chv_config_set_pull()
1072 		ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;  in chv_config_set_pull()
1076 		ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);  in chv_config_set_pull()
1090 		ctrl0 |= pull;  in chv_config_set_pull()
1098 	chv_writel(ctrl0, reg);  in chv_config_set_pull()
1172 	u32 ctrl0, cfg;  in chv_gpio_get()  local
1174 	ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));  in chv_gpio_get()
1176 	cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;  in chv_gpio_get()
1180 		return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);  in chv_gpio_get()
1181 	return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);  in chv_gpio_get()
1190 	u32 ctrl0;  in chv_gpio_set()  local
1195 	ctrl0 = readl(reg);  in chv_gpio_set()
1198 		ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;  in chv_gpio_set()
1200 		ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;  in chv_gpio_set()
1202 	chv_writel(ctrl0, reg);  in chv_gpio_set()
1211 	u32 ctrl0, direction;  in chv_gpio_get_direction()  local
1213 	ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));  in chv_gpio_get_direction()
1215 	direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;  in chv_gpio_get_direction()