Lines Matching refs:writeb_relaxed
374 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
377 writeb_relaxed(val, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
379 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset()
384 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset()
387 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset()
398 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); in miphy28lp_pll_calibration()
399 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
402 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
403 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
404 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); in miphy28lp_pll_calibration()
405 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); in miphy28lp_pll_calibration()
406 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); in miphy28lp_pll_calibration()
408 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); in miphy28lp_pll_calibration()
411 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); in miphy28lp_pll_calibration()
418 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); in miphy28lp_pll_calibration()
421 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_pll_calibration()
422 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); in miphy28lp_pll_calibration()
423 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); in miphy28lp_pll_calibration()
424 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); in miphy28lp_pll_calibration()
425 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); in miphy28lp_pll_calibration()
428 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); in miphy28lp_pll_calibration()
442 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_sata_config_gen()
443 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_sata_config_gen()
444 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_sata_config_gen()
445 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_sata_config_gen()
448 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_sata_config_gen()
449 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_sata_config_gen()
452 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_sata_config_gen()
453 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_sata_config_gen()
454 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_sata_config_gen()
455 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_sata_config_gen()
456 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); in miphy28lp_sata_config_gen()
469 writeb_relaxed(gen->bank, base + MIPHY_CONF); in miphy28lp_pcie_config_gen()
470 writeb_relaxed(gen->speed, base + MIPHY_SPEED); in miphy28lp_pcie_config_gen()
471 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); in miphy28lp_pcie_config_gen()
472 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); in miphy28lp_pcie_config_gen()
475 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); in miphy28lp_pcie_config_gen()
476 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); in miphy28lp_pcie_config_gen()
477 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); in miphy28lp_pcie_config_gen()
479 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); in miphy28lp_pcie_config_gen()
482 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_pcie_config_gen()
483 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); in miphy28lp_pcie_config_gen()
484 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_pcie_config_gen()
485 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); in miphy28lp_pcie_config_gen()
514 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); in miphy28lp_compensation()
516 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); in miphy28lp_compensation()
517 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_compensation()
518 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); in miphy28lp_compensation()
521 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); in miphy28lp_compensation()
523 writeb_relaxed(0x00, base + MIPHY_RESET); in miphy28lp_compensation()
524 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); in miphy28lp_compensation()
525 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy28lp_compensation()
528 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); in miphy28lp_compensation()
542 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28_usb3_miphy_reset()
543 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28_usb3_miphy_reset()
544 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
547 writeb_relaxed(val, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
549 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); in miphy28_usb3_miphy_reset()
550 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); in miphy28_usb3_miphy_reset()
551 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); in miphy28_usb3_miphy_reset()
552 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
553 writeb_relaxed(0x00, base + MIPHY_RESET); in miphy28_usb3_miphy_reset()
554 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); in miphy28_usb3_miphy_reset()
555 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
556 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); in miphy28_usb3_miphy_reset()
557 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); in miphy28_usb3_miphy_reset()
558 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
559 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy28_usb3_miphy_reset()
560 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); in miphy28_usb3_miphy_reset()
561 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28_usb3_miphy_reset()
576 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); in miphy_sata_tune_ssc()
580 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy_sata_tune_ssc()
583 writeb_relaxed(val, base + MIPHY_CONF); in miphy_sata_tune_ssc()
587 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy_sata_tune_ssc()
588 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); in miphy_sata_tune_ssc()
589 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); in miphy_sata_tune_ssc()
592 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
595 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
598 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_sata_tune_ssc()
614 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); in miphy_pcie_tune_ssc()
618 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy_pcie_tune_ssc()
621 writeb_relaxed(val, base + MIPHY_CONF); in miphy_pcie_tune_ssc()
624 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); in miphy_pcie_tune_ssc()
625 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); in miphy_pcie_tune_ssc()
628 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy_pcie_tune_ssc()
629 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); in miphy_pcie_tune_ssc()
632 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
635 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
638 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy_pcie_tune_ssc()
645 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); in miphy_tune_tx_impedance()
665 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_sata()
668 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28lp_configure_sata()
680 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); in miphy28lp_configure_sata()
708 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_pcie()
711 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); in miphy28lp_configure_pcie()
741 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_configure_usb3()
744 writeb_relaxed(val, base + MIPHY_SPEED); in miphy28lp_configure_usb3()
747 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); in miphy28lp_configure_usb3()
748 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); in miphy28lp_configure_usb3()
749 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); in miphy28lp_configure_usb3()
753 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); in miphy28lp_configure_usb3()
754 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); in miphy28lp_configure_usb3()
755 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); in miphy28lp_configure_usb3()
758 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); in miphy28lp_configure_usb3()
759 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); in miphy28lp_configure_usb3()
760 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); in miphy28lp_configure_usb3()
763 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); in miphy28lp_configure_usb3()
768 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); in miphy28lp_configure_usb3()
771 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); in miphy28lp_configure_usb3()
772 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); in miphy28lp_configure_usb3()
775 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); in miphy28lp_configure_usb3()
778 writeb_relaxed(0x00, base + MIPHY_CONF); in miphy28lp_configure_usb3()
781 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); in miphy28lp_configure_usb3()
782 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); in miphy28lp_configure_usb3()
785 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); in miphy28lp_configure_usb3()
786 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); in miphy28lp_configure_usb3()
789 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
792 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
795 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); in miphy28lp_configure_usb3()
798 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); in miphy28lp_configure_usb3()
802 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_usb3()
803 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); in miphy28lp_configure_usb3()
804 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); in miphy28lp_configure_usb3()
992 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ in miphy28lp_init_pcie()
993 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ in miphy28lp_init_pcie()
994 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ in miphy28lp_init_pcie()
995 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ in miphy28lp_init_pcie()
996 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ in miphy28lp_init_pcie()
997 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ in miphy28lp_init_pcie()
1024 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); in miphy28lp_init_usb3()
1025 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); in miphy28lp_init_usb3()
1026 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); in miphy28lp_init_usb3()
1027 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); in miphy28lp_init_usb3()
1028 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); in miphy28lp_init_usb3()
1029 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); in miphy28lp_init_usb3()
1032 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); in miphy28lp_init_usb3()
1033 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); in miphy28lp_init_usb3()
1034 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); in miphy28lp_init_usb3()
1035 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); in miphy28lp_init_usb3()
1036 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); in miphy28lp_init_usb3()
1037 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); in miphy28lp_init_usb3()
1038 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); in miphy28lp_init_usb3()
1039 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); in miphy28lp_init_usb3()