Lines Matching refs:dev
62 static int find_anything(struct device *dev, void *data) in find_anything() argument
74 struct device *dev; in no_pci_devices() local
77 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); in no_pci_devices()
78 no_devices = (dev == NULL); in no_pci_devices()
79 put_device(dev); in no_pci_devices()
87 static void release_pcibus_dev(struct device *dev) in release_pcibus_dev() argument
89 struct pci_bus *pci_bus = to_pci_bus(dev); in release_pcibus_dev()
127 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) in decode_bar() argument
171 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, in __pci_read_base() argument
182 if (!dev->mmio_always_on) { in __pci_read_base()
183 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); in __pci_read_base()
185 pci_write_config_word(dev, PCI_COMMAND, in __pci_read_base()
190 res->name = pci_name(dev); in __pci_read_base()
192 pci_read_config_dword(dev, pos, &l); in __pci_read_base()
193 pci_write_config_dword(dev, pos, l | mask); in __pci_read_base()
194 pci_read_config_dword(dev, pos, &sz); in __pci_read_base()
195 pci_write_config_dword(dev, pos, l); in __pci_read_base()
214 res->flags = decode_bar(dev, l); in __pci_read_base()
233 pci_read_config_dword(dev, pos + 4, &l); in __pci_read_base()
234 pci_write_config_dword(dev, pos + 4, ~0); in __pci_read_base()
235 pci_read_config_dword(dev, pos + 4, &sz); in __pci_read_base()
236 pci_write_config_dword(dev, pos + 4, l); in __pci_read_base()
243 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) in __pci_read_base()
244 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); in __pci_read_base()
251 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n", in __pci_read_base()
262 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", in __pci_read_base()
272 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n", in __pci_read_base()
281 pcibios_bus_to_resource(dev->bus, res, ®ion); in __pci_read_base()
282 pcibios_resource_to_bus(dev->bus, &inverted_region, res); in __pci_read_base()
299 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", in __pci_read_base()
310 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); in __pci_read_base()
315 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) in pci_read_bases() argument
319 if (dev->non_compliant_bars) in pci_read_bases()
323 struct resource *res = &dev->resource[pos]; in pci_read_bases()
325 pos += __pci_read_base(dev, pci_bar_unknown, res, reg); in pci_read_bases()
329 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; in pci_read_bases()
330 dev->rom_base_reg = rom; in pci_read_bases()
334 __pci_read_base(dev, pci_bar_mem32, res, rom); in pci_read_bases()
340 struct pci_dev *dev = child->self; in pci_read_bridge_io() local
348 if (dev->io_window_1k) { in pci_read_bridge_io()
355 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); in pci_read_bridge_io()
356 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); in pci_read_bridge_io()
363 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); in pci_read_bridge_io()
364 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); in pci_read_bridge_io()
373 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_io()
374 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_io()
380 struct pci_dev *dev = child->self; in pci_read_bridge_mmio() local
387 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio()
388 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio()
395 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio()
396 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_mmio()
402 struct pci_dev *dev = child->self; in pci_read_bridge_mmio_pref() local
410 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); in pci_read_bridge_mmio_pref()
411 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); in pci_read_bridge_mmio_pref()
418 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); in pci_read_bridge_mmio_pref()
419 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); in pci_read_bridge_mmio_pref()
436 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", in pci_read_bridge_mmio_pref()
448 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_read_bridge_mmio_pref()
449 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); in pci_read_bridge_mmio_pref()
455 struct pci_dev *dev = child->self; in pci_read_bridge_bases() local
462 dev_info(&dev->dev, "PCI bridge to %pR%s\n", in pci_read_bridge_bases()
464 dev->transparent ? " (subtractive decode)" : ""); in pci_read_bridge_bases()
468 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; in pci_read_bridge_bases()
474 if (dev->transparent) { in pci_read_bridge_bases()
479 dev_printk(KERN_DEBUG, &dev->dev, in pci_read_bridge_bases()
509 static void pci_release_host_bridge_dev(struct device *dev) in pci_release_host_bridge_dev() argument
511 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); in pci_release_host_bridge_dev()
690 child->dev.class = &pcibus_class; in pci_alloc_child_bus()
691 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); in pci_alloc_child_bus()
702 child->dev.parent = parent->bridge; in pci_alloc_child_bus()
707 child->bridge = get_device(&bridge->dev); in pci_alloc_child_bus()
708 child->dev.parent = child->bridge; in pci_alloc_child_bus()
720 ret = device_register(&child->dev); in pci_alloc_child_bus()
731 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, in pci_add_new_bus() argument
736 child = pci_alloc_child_bus(parent, dev, busnr); in pci_add_new_bus()
767 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) in pci_scan_bridge() argument
770 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); in pci_scan_bridge()
776 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); in pci_scan_bridge()
781 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", in pci_scan_bridge()
785 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); in pci_scan_bridge()
793 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", in pci_scan_bridge()
800 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); in pci_scan_bridge()
801 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, in pci_scan_bridge()
804 pci_enable_crs(dev); in pci_scan_bridge()
824 child = pci_add_new_bus(bus, dev, secondary); in pci_scan_bridge()
834 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", in pci_scan_bridge()
852 pci_write_config_dword(dev, PCI_PRIMARY_BUS, in pci_scan_bridge()
858 pci_write_config_word(dev, PCI_STATUS, 0xffff); in pci_scan_bridge()
865 child = pci_add_new_bus(bus, dev, max+1); in pci_scan_bridge()
888 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); in pci_scan_bridge()
928 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); in pci_scan_bridge()
941 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", in pci_scan_bridge()
947 dev_name(&bus->dev), in pci_scan_bridge()
954 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); in pci_scan_bridge()
964 static void pci_read_irq(struct pci_dev *dev) in pci_read_irq() argument
968 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); in pci_read_irq()
969 dev->pin = irq; in pci_read_irq()
971 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); in pci_read_irq()
972 dev->irq = irq; in pci_read_irq()
1033 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) in pci_ext_cfg_is_aliased() argument
1039 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); in pci_ext_cfg_is_aliased()
1043 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL in pci_ext_cfg_is_aliased()
1065 static int pci_cfg_space_size_ext(struct pci_dev *dev) in pci_cfg_space_size_ext() argument
1070 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) in pci_cfg_space_size_ext()
1072 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) in pci_cfg_space_size_ext()
1081 int pci_cfg_space_size(struct pci_dev *dev) in pci_cfg_space_size() argument
1087 class = dev->class >> 8; in pci_cfg_space_size()
1089 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1091 if (!pci_is_pcie(dev)) { in pci_cfg_space_size()
1092 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); in pci_cfg_space_size()
1096 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); in pci_cfg_space_size()
1101 return pci_cfg_space_size_ext(dev); in pci_cfg_space_size()
1119 int pci_setup_device(struct pci_dev *dev) in pci_setup_device() argument
1129 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) in pci_setup_device()
1132 dev->sysdata = dev->bus->sysdata; in pci_setup_device()
1133 dev->dev.parent = dev->bus->bridge; in pci_setup_device()
1134 dev->dev.bus = &pci_bus_type; in pci_setup_device()
1135 dev->hdr_type = hdr_type & 0x7f; in pci_setup_device()
1136 dev->multifunction = !!(hdr_type & 0x80); in pci_setup_device()
1137 dev->error_state = pci_channel_io_normal; in pci_setup_device()
1138 set_pcie_port_type(dev); in pci_setup_device()
1140 list_for_each_entry(slot, &dev->bus->slots, list) in pci_setup_device()
1141 if (PCI_SLOT(dev->devfn) == slot->number) in pci_setup_device()
1142 dev->slot = slot; in pci_setup_device()
1146 dev->dma_mask = 0xffffffff; in pci_setup_device()
1148 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), in pci_setup_device()
1149 dev->bus->number, PCI_SLOT(dev->devfn), in pci_setup_device()
1150 PCI_FUNC(dev->devfn)); in pci_setup_device()
1152 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); in pci_setup_device()
1153 dev->revision = class & 0xff; in pci_setup_device()
1154 dev->class = class >> 8; /* upper 3 bytes */ in pci_setup_device()
1156 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", in pci_setup_device()
1157 dev->vendor, dev->device, dev->hdr_type, dev->class); in pci_setup_device()
1160 dev->cfg_size = pci_cfg_space_size(dev); in pci_setup_device()
1163 dev->current_state = PCI_UNKNOWN; in pci_setup_device()
1166 pci_fixup_device(pci_fixup_early, dev); in pci_setup_device()
1168 class = dev->class >> 8; in pci_setup_device()
1170 if (dev->non_compliant_bars) { in pci_setup_device()
1171 pci_read_config_word(dev, PCI_COMMAND, &cmd); in pci_setup_device()
1173 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); in pci_setup_device()
1176 pci_write_config_word(dev, PCI_COMMAND, cmd); in pci_setup_device()
1180 switch (dev->hdr_type) { /* header type */ in pci_setup_device()
1184 pci_read_irq(dev); in pci_setup_device()
1185 pci_read_bases(dev, 6, PCI_ROM_ADDRESS); in pci_setup_device()
1186 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1187 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1197 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); in pci_setup_device()
1201 res = &dev->resource[0]; in pci_setup_device()
1203 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1204 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", in pci_setup_device()
1208 res = &dev->resource[1]; in pci_setup_device()
1210 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1211 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", in pci_setup_device()
1217 res = &dev->resource[2]; in pci_setup_device()
1219 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1220 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", in pci_setup_device()
1224 res = &dev->resource[3]; in pci_setup_device()
1226 pcibios_bus_to_resource(dev->bus, res, ®ion); in pci_setup_device()
1227 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", in pci_setup_device()
1239 pci_read_irq(dev); in pci_setup_device()
1240 dev->transparent = ((dev->class & 0xff) == 1); in pci_setup_device()
1241 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); in pci_setup_device()
1242 set_pcie_hotplug_bridge(dev); in pci_setup_device()
1243 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); in pci_setup_device()
1245 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1246 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); in pci_setup_device()
1253 pci_read_irq(dev); in pci_setup_device()
1254 pci_read_bases(dev, 1, 0); in pci_setup_device()
1255 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); in pci_setup_device()
1256 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); in pci_setup_device()
1260 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", in pci_setup_device()
1261 dev->hdr_type); in pci_setup_device()
1265 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", in pci_setup_device()
1266 dev->class, dev->hdr_type); in pci_setup_device()
1267 dev->class = PCI_CLASS_NOT_DEFINED; in pci_setup_device()
1282 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) in program_hpp_type0() argument
1290 dev_warn(&dev->dev, in program_hpp_type0()
1296 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); in program_hpp_type0()
1297 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); in program_hpp_type0()
1298 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); in program_hpp_type0()
1303 pci_write_config_word(dev, PCI_COMMAND, pci_cmd); in program_hpp_type0()
1306 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { in program_hpp_type0()
1307 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, in program_hpp_type0()
1309 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); in program_hpp_type0()
1314 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); in program_hpp_type0()
1318 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) in program_hpp_type1() argument
1321 dev_warn(&dev->dev, "PCI-X settings not supported\n"); in program_hpp_type1()
1324 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) in program_hpp_type2() argument
1333 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", in program_hpp_type2()
1349 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, in program_hpp_type2()
1353 if (pcie_cap_has_lnkctl(dev)) in program_hpp_type2()
1354 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, in program_hpp_type2()
1358 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); in program_hpp_type2()
1363 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); in program_hpp_type2()
1365 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpp_type2()
1368 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); in program_hpp_type2()
1370 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpp_type2()
1373 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); in program_hpp_type2()
1375 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpp_type2()
1378 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); in program_hpp_type2()
1380 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); in program_hpp_type2()
1390 static void pci_configure_device(struct pci_dev *dev) in pci_configure_device() argument
1396 ret = pci_get_hp_params(dev, &hpp); in pci_configure_device()
1400 program_hpp_type2(dev, hpp.t2); in pci_configure_device()
1401 program_hpp_type1(dev, hpp.t1); in pci_configure_device()
1402 program_hpp_type0(dev, hpp.t0); in pci_configure_device()
1405 static void pci_release_capabilities(struct pci_dev *dev) in pci_release_capabilities() argument
1407 pci_vpd_release(dev); in pci_release_capabilities()
1408 pci_iov_release(dev); in pci_release_capabilities()
1409 pci_free_cap_save_buffers(dev); in pci_release_capabilities()
1419 static void pci_release_dev(struct device *dev) in pci_release_dev() argument
1423 pci_dev = to_pci_dev(dev); in pci_release_dev()
1434 struct pci_dev *dev; in pci_alloc_dev() local
1436 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); in pci_alloc_dev()
1437 if (!dev) in pci_alloc_dev()
1440 INIT_LIST_HEAD(&dev->bus_list); in pci_alloc_dev()
1441 dev->dev.type = &pci_dev_type; in pci_alloc_dev()
1442 dev->bus = pci_bus_get(bus); in pci_alloc_dev()
1444 return dev; in pci_alloc_dev()
1494 struct pci_dev *dev; in pci_scan_device() local
1500 dev = pci_alloc_dev(bus); in pci_scan_device()
1501 if (!dev) in pci_scan_device()
1504 dev->devfn = devfn; in pci_scan_device()
1505 dev->vendor = l & 0xffff; in pci_scan_device()
1506 dev->device = (l >> 16) & 0xffff; in pci_scan_device()
1508 pci_set_of_node(dev); in pci_scan_device()
1510 if (pci_setup_device(dev)) { in pci_scan_device()
1511 pci_bus_put(dev->bus); in pci_scan_device()
1512 kfree(dev); in pci_scan_device()
1516 return dev; in pci_scan_device()
1519 static void pci_init_capabilities(struct pci_dev *dev) in pci_init_capabilities() argument
1522 pci_msi_init_pci_dev(dev); in pci_init_capabilities()
1525 pci_allocate_cap_save_buffers(dev); in pci_init_capabilities()
1528 pci_pm_init(dev); in pci_init_capabilities()
1531 pci_vpd_pci22_init(dev); in pci_init_capabilities()
1534 pci_configure_ari(dev); in pci_init_capabilities()
1537 pci_iov_init(dev); in pci_init_capabilities()
1540 pci_enable_acs(dev); in pci_init_capabilities()
1543 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) in pci_device_add() argument
1547 pci_configure_device(dev); in pci_device_add()
1549 device_initialize(&dev->dev); in pci_device_add()
1550 dev->dev.release = pci_release_dev; in pci_device_add()
1552 set_dev_node(&dev->dev, pcibus_to_node(bus)); in pci_device_add()
1553 dev->dev.dma_mask = &dev->dma_mask; in pci_device_add()
1554 dev->dev.dma_parms = &dev->dma_parms; in pci_device_add()
1555 dev->dev.coherent_dma_mask = 0xffffffffull; in pci_device_add()
1556 of_pci_dma_configure(dev); in pci_device_add()
1558 pci_set_dma_max_seg_size(dev, 65536); in pci_device_add()
1559 pci_set_dma_seg_boundary(dev, 0xffffffff); in pci_device_add()
1562 pci_fixup_device(pci_fixup_header, dev); in pci_device_add()
1565 pci_reassigndev_resource_alignment(dev); in pci_device_add()
1568 dev->state_saved = false; in pci_device_add()
1571 pci_init_capabilities(dev); in pci_device_add()
1578 list_add_tail(&dev->bus_list, &bus->devices); in pci_device_add()
1581 ret = pcibios_add_device(dev); in pci_device_add()
1585 dev->match_driver = false; in pci_device_add()
1586 ret = device_add(&dev->dev); in pci_device_add()
1592 struct pci_dev *dev; in pci_scan_single_device() local
1594 dev = pci_get_slot(bus, devfn); in pci_scan_single_device()
1595 if (dev) { in pci_scan_single_device()
1596 pci_dev_put(dev); in pci_scan_single_device()
1597 return dev; in pci_scan_single_device()
1600 dev = pci_scan_device(bus, devfn); in pci_scan_single_device()
1601 if (!dev) in pci_scan_single_device()
1604 pci_device_add(dev, bus); in pci_scan_single_device()
1606 return dev; in pci_scan_single_device()
1610 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) in next_fn() argument
1617 if (!dev) in next_fn()
1619 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); in next_fn()
1623 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); in next_fn()
1632 if (!dev || dev->multifunction) in next_fn()
1666 struct pci_dev *dev; in pci_scan_slot() local
1671 dev = pci_scan_single_device(bus, devfn); in pci_scan_slot()
1672 if (!dev) in pci_scan_slot()
1674 if (!dev->is_added) in pci_scan_slot()
1677 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { in pci_scan_slot()
1678 dev = pci_scan_single_device(bus, devfn + fn); in pci_scan_slot()
1679 if (dev) { in pci_scan_slot()
1680 if (!dev->is_added) in pci_scan_slot()
1682 dev->multifunction = 1; in pci_scan_slot()
1694 static int pcie_find_smpss(struct pci_dev *dev, void *data) in pcie_find_smpss() argument
1698 if (!pci_is_pcie(dev)) in pcie_find_smpss()
1716 if (dev->is_hotplug_bridge && in pcie_find_smpss()
1717 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) in pcie_find_smpss()
1720 if (*smpss > dev->pcie_mpss) in pcie_find_smpss()
1721 *smpss = dev->pcie_mpss; in pcie_find_smpss()
1726 static void pcie_write_mps(struct pci_dev *dev, int mps) in pcie_write_mps() argument
1731 mps = 128 << dev->pcie_mpss; in pcie_write_mps()
1733 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && in pcie_write_mps()
1734 dev->bus->self) in pcie_write_mps()
1747 mps = min(mps, pcie_get_mps(dev->bus->self)); in pcie_write_mps()
1750 rc = pcie_set_mps(dev, mps); in pcie_write_mps()
1752 dev_err(&dev->dev, "Failed attempting to set the MPS\n"); in pcie_write_mps()
1755 static void pcie_write_mrrs(struct pci_dev *dev) in pcie_write_mrrs() argument
1770 mrrs = pcie_get_mps(dev); in pcie_write_mrrs()
1777 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { in pcie_write_mrrs()
1778 rc = pcie_set_readrq(dev, mrrs); in pcie_write_mrrs()
1782 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); in pcie_write_mrrs()
1787 …dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienc… in pcie_write_mrrs()
1790 static void pcie_bus_detect_mps(struct pci_dev *dev) in pcie_bus_detect_mps() argument
1792 struct pci_dev *bridge = dev->bus->self; in pcie_bus_detect_mps()
1798 mps = pcie_get_mps(dev); in pcie_bus_detect_mps()
1802 …dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_… in pcie_bus_detect_mps()
1806 static int pcie_bus_configure_set(struct pci_dev *dev, void *data) in pcie_bus_configure_set() argument
1810 if (!pci_is_pcie(dev)) in pcie_bus_configure_set()
1814 pcie_bus_detect_mps(dev); in pcie_bus_configure_set()
1819 orig_mps = pcie_get_mps(dev); in pcie_bus_configure_set()
1821 pcie_write_mps(dev, mps); in pcie_bus_configure_set()
1822 pcie_write_mrrs(dev); in pcie_bus_configure_set()
1824 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", in pcie_bus_configure_set()
1825 pcie_get_mps(dev), 128 << dev->pcie_mpss, in pcie_bus_configure_set()
1826 orig_mps, pcie_get_readrq(dev)); in pcie_bus_configure_set()
1867 struct pci_dev *dev; in pci_scan_child_bus() local
1869 dev_dbg(&bus->dev, "scanning bus\n"); in pci_scan_child_bus()
1883 dev_dbg(&bus->dev, "fixups for bus\n"); in pci_scan_child_bus()
1889 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_scan_child_bus()
1890 if (pci_is_bridge(dev)) in pci_scan_child_bus()
1891 max = pci_scan_bridge(bus, dev, max, pass); in pci_scan_child_bus()
1901 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); in pci_scan_child_bus()
1949 dev_dbg(&b2->dev, "bus already known\n"); in pci_create_root_bus()
1957 bridge->dev.parent = parent; in pci_create_root_bus()
1958 bridge->dev.release = pci_release_host_bridge_dev; in pci_create_root_bus()
1959 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); in pci_create_root_bus()
1966 error = device_register(&bridge->dev); in pci_create_root_bus()
1968 put_device(&bridge->dev); in pci_create_root_bus()
1971 b->bridge = get_device(&bridge->dev); in pci_create_root_bus()
1978 b->dev.class = &pcibus_class; in pci_create_root_bus()
1979 b->dev.parent = b->bridge; in pci_create_root_bus()
1980 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); in pci_create_root_bus()
1981 error = device_register(&b->dev); in pci_create_root_bus()
1991 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); in pci_create_root_bus()
1993 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); in pci_create_root_bus()
2014 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); in pci_create_root_bus()
2024 put_device(&bridge->dev); in pci_create_root_bus()
2025 device_unregister(&bridge->dev); in pci_create_root_bus()
2051 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_insert_busn_res()
2071 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_update_busn_res_end()
2090 dev_printk(KERN_DEBUG, &b->dev, in pci_bus_release_busn_res()
2114 dev_info(&b->dev, in pci_scan_root_bus()