124 	struct msi_desc *entry;  in arch_setup_msi_irqs()  local
134 	list_for_each_entry(entry, &dev->msi_list, list) {  in arch_setup_msi_irqs()
135 		ret = arch_setup_msi_irq(dev, entry);  in arch_setup_msi_irqs()
152 	struct msi_desc *entry;  in default_teardown_msi_irqs()  local
154 	list_for_each_entry(entry, &dev->msi_list, list)  in default_teardown_msi_irqs()
155 		if (entry->irq)  in default_teardown_msi_irqs()
156 			for (i = 0; i < entry->nvec_used; i++)  in default_teardown_msi_irqs()
157 				arch_teardown_msi_irq(entry->irq + i);  in default_teardown_msi_irqs()
167 	struct msi_desc *entry;  in default_restore_msi_irq()  local
169 	entry = NULL;  in default_restore_msi_irq()
171 		list_for_each_entry(entry, &dev->msi_list, list) {  in default_restore_msi_irq()
172 			if (irq == entry->irq)  in default_restore_msi_irq()
176 		entry = irq_get_msi_desc(irq);  in default_restore_msi_irq()
179 	if (entry)  in default_restore_msi_irq()
180 		__pci_write_msi_msg(entry, &entry->msg);  in default_restore_msi_irq()
304 	struct msi_desc *entry;  in default_restore_msi_irqs()  local
306 	list_for_each_entry(entry, &dev->msi_list, list)  in default_restore_msi_irqs()
307 		default_restore_msi_irq(dev, entry->irq);  in default_restore_msi_irqs()
310 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)  in __pci_read_msi_msg()  argument
312 	BUG_ON(entry->dev->current_state != PCI_D0);  in __pci_read_msi_msg()
314 	if (entry->msi_attrib.is_msix) {  in __pci_read_msi_msg()
315 		void __iomem *base = entry->mask_base +  in __pci_read_msi_msg()
316 			entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;  in __pci_read_msi_msg()
322 		struct pci_dev *dev = entry->dev;  in __pci_read_msi_msg()
328 		if (entry->msi_attrib.is_64) {  in __pci_read_msi_msg()
340 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)  in __pci_write_msi_msg()  argument
342 	if (entry->dev->current_state != PCI_D0) {  in __pci_write_msi_msg()
344 	} else if (entry->msi_attrib.is_msix) {  in __pci_write_msi_msg()
346 		base = entry->mask_base +  in __pci_write_msi_msg()
347 			entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;  in __pci_write_msi_msg()
353 		struct pci_dev *dev = entry->dev;  in __pci_write_msi_msg()
359 		msgctl |= entry->msi_attrib.multiple << 4;  in __pci_write_msi_msg()
364 		if (entry->msi_attrib.is_64) {  in __pci_write_msi_msg()
374 	entry->msg = *msg;  in __pci_write_msi_msg()
379 	struct msi_desc *entry = irq_get_msi_desc(irq);  in pci_write_msi_msg()  local
381 	__pci_write_msi_msg(entry, msg);  in pci_write_msi_msg()
387 	struct msi_desc *entry, *tmp;  in free_msi_irqs()  local
392 	list_for_each_entry(entry, &dev->msi_list, list)  in free_msi_irqs()
393 		if (entry->irq)  in free_msi_irqs()
394 			for (i = 0; i < entry->nvec_used; i++)  in free_msi_irqs()
395 				BUG_ON(irq_has_action(entry->irq + i));  in free_msi_irqs()
399 	list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {  in free_msi_irqs()
400 		if (entry->msi_attrib.is_msix) {  in free_msi_irqs()
401 			if (list_is_last(&entry->list, &dev->msi_list))  in free_msi_irqs()
402 				iounmap(entry->mask_base);  in free_msi_irqs()
405 		list_del(&entry->list);  in free_msi_irqs()
406 		kfree(entry);  in free_msi_irqs()
447 	struct msi_desc *entry;  in __pci_restore_msi_state()  local
452 	entry = irq_get_msi_desc(dev->irq);  in __pci_restore_msi_state()
459 	msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),  in __pci_restore_msi_state()
460 		     entry->masked);  in __pci_restore_msi_state()
462 	control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;  in __pci_restore_msi_state()
468 	struct msi_desc *entry;  in __pci_restore_msix_state()  local
480 	list_for_each_entry(entry, &dev->msi_list, list)  in __pci_restore_msix_state()
481 		msix_mask_irq(entry, entry->masked);  in __pci_restore_msix_state()
496 	struct msi_desc *entry;  in msi_mode_show()  local
504 	entry = irq_get_msi_desc(irq);  in msi_mode_show()
505 	if (entry)  in msi_mode_show()
507 				entry->msi_attrib.is_msix ? "msix" : "msi");  in msi_mode_show()
519 	struct msi_desc *entry;  in populate_msi_sysfs()  local
525 	list_for_each_entry(entry, &pdev->msi_list, list)  in populate_msi_sysfs()
534 	list_for_each_entry(entry, &pdev->msi_list, list) {  in populate_msi_sysfs()
542 						    entry->irq);  in populate_msi_sysfs()
589 	struct msi_desc *entry;  in msi_setup_entry()  local
592 	entry = alloc_msi_entry(dev);  in msi_setup_entry()
593 	if (!entry)  in msi_setup_entry()
598 	entry->msi_attrib.is_msix	= 0;  in msi_setup_entry()
599 	entry->msi_attrib.is_64		= !!(control & PCI_MSI_FLAGS_64BIT);  in msi_setup_entry()
600 	entry->msi_attrib.entry_nr	= 0;  in msi_setup_entry()
601 	entry->msi_attrib.maskbit	= !!(control & PCI_MSI_FLAGS_MASKBIT);  in msi_setup_entry()
602 	entry->msi_attrib.default_irq	= dev->irq;	/* Save IOAPIC IRQ */  in msi_setup_entry()
603 	entry->msi_attrib.multi_cap	= (control & PCI_MSI_FLAGS_QMASK) >> 1;  in msi_setup_entry()
604 	entry->msi_attrib.multiple	= ilog2(__roundup_pow_of_two(nvec));  in msi_setup_entry()
605 	entry->nvec_used		= nvec;  in msi_setup_entry()
608 		entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;  in msi_setup_entry()
610 		entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;  in msi_setup_entry()
613 	if (entry->msi_attrib.maskbit)  in msi_setup_entry()
614 		pci_read_config_dword(dev, entry->mask_pos, &entry->masked);  in msi_setup_entry()
616 	return entry;  in msi_setup_entry()
621 	struct msi_desc *entry;  in msi_verify_entries()  local
623 	list_for_each_entry(entry, &dev->msi_list, list) {  in msi_verify_entries()
624 		if (!dev->no_64bit_msi || !entry->msg.address_hi)  in msi_verify_entries()
646 	struct msi_desc *entry;  in msi_capability_init()  local
652 	entry = msi_setup_entry(dev, nvec);  in msi_capability_init()
653 	if (!entry)  in msi_capability_init()
657 	mask = msi_mask(entry->msi_attrib.multi_cap);  in msi_capability_init()
658 	msi_mask_irq(entry, mask, mask);  in msi_capability_init()
660 	list_add_tail(&entry->list, &dev->msi_list);  in msi_capability_init()
665 		msi_mask_irq(entry, mask, ~mask);  in msi_capability_init()
672 		msi_mask_irq(entry, mask, ~mask);  in msi_capability_init()
679 		msi_mask_irq(entry, mask, ~mask);  in msi_capability_init()
689 	dev->irq = entry->irq;  in msi_capability_init()
716 	struct msi_desc *entry;  in msix_setup_entries()  local
720 		entry = alloc_msi_entry(dev);  in msix_setup_entries()
721 		if (!entry) {  in msix_setup_entries()
730 		entry->msi_attrib.is_msix	= 1;  in msix_setup_entries()
731 		entry->msi_attrib.is_64		= 1;  in msix_setup_entries()
732 		entry->msi_attrib.entry_nr	= entries[i].entry;  in msix_setup_entries()
733 		entry->msi_attrib.default_irq	= dev->irq;  in msix_setup_entries()
734 		entry->mask_base		= base;  in msix_setup_entries()
735 		entry->nvec_used		= 1;  in msix_setup_entries()
737 		list_add_tail(&entry->list, &dev->msi_list);  in msix_setup_entries()
746 	struct msi_desc *entry;  in msix_program_entries()  local
749 	list_for_each_entry(entry, &dev->msi_list, list) {  in msix_program_entries()
750 		int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +  in msix_program_entries()
753 		entries[i].vector = entry->irq;  in msix_program_entries()
754 		entry->masked = readl(entry->mask_base + offset);  in msix_program_entries()
755 		msix_mask_irq(entry, 1);  in msix_program_entries()
827 		struct msi_desc *entry;  in msix_capability_init()  local
830 		list_for_each_entry(entry, &dev->msi_list, list) {  in msix_capability_init()
831 			if (entry->irq != 0)  in msix_capability_init()
999 		if (entries[i].entry >= nr_entries)  in pci_enable_msix()
1002 			if (entries[i].entry == entries[j].entry)  in pci_enable_msix()
1019 	struct msi_desc *entry;  in pci_msix_shutdown()  local
1025 	list_for_each_entry(entry, &dev->msi_list, list) {  in pci_msix_shutdown()
1027 		__pci_msix_desc_mask_irq(entry, 1);  in pci_msix_shutdown()