114 	u32 port;  member
135 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)  in mvebu_writel()  argument
137 	writel(val, port->base + reg);  in mvebu_writel()
140 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)  in mvebu_readl()  argument
142 	return readl(port->base + reg);  in mvebu_readl()
145 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)  in mvebu_has_ioport()  argument
147 	return port->io_target != -1 && port->io_attr != -1;  in mvebu_has_ioport()
150 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)  in mvebu_pcie_link_up()  argument
152 	return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);  in mvebu_pcie_link_up()
155 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)  in mvebu_pcie_set_local_bus_nr()  argument
159 	stat = mvebu_readl(port, PCIE_STAT_OFF);  in mvebu_pcie_set_local_bus_nr()
162 	mvebu_writel(port, stat, PCIE_STAT_OFF);  in mvebu_pcie_set_local_bus_nr()
165 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)  in mvebu_pcie_set_local_dev_nr()  argument
169 	stat = mvebu_readl(port, PCIE_STAT_OFF);  in mvebu_pcie_set_local_dev_nr()
172 	mvebu_writel(port, stat, PCIE_STAT_OFF);  in mvebu_pcie_set_local_dev_nr()
180 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)  in mvebu_pcie_setup_wins()  argument
190 		mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));  in mvebu_pcie_setup_wins()
191 		mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));  in mvebu_pcie_setup_wins()
192 		mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));  in mvebu_pcie_setup_wins()
196 		mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));  in mvebu_pcie_setup_wins()
197 		mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));  in mvebu_pcie_setup_wins()
198 		mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));  in mvebu_pcie_setup_wins()
201 	mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);  in mvebu_pcie_setup_wins()
202 	mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);  in mvebu_pcie_setup_wins()
203 	mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);  in mvebu_pcie_setup_wins()
210 		mvebu_writel(port, cs->base & 0xffff0000,  in mvebu_pcie_setup_wins()
212 		mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));  in mvebu_pcie_setup_wins()
213 		mvebu_writel(port,  in mvebu_pcie_setup_wins()
227 	mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));  in mvebu_pcie_setup_wins()
228 	mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));  in mvebu_pcie_setup_wins()
229 	mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,  in mvebu_pcie_setup_wins()
233 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)  in mvebu_pcie_setup_hw()  argument
238 	mvebu_pcie_setup_wins(port);  in mvebu_pcie_setup_hw()
241 	cmd = mvebu_readl(port, PCIE_CMD_OFF);  in mvebu_pcie_setup_hw()
245 	mvebu_writel(port, cmd, PCIE_CMD_OFF);  in mvebu_pcie_setup_hw()
248 	mask = mvebu_readl(port, PCIE_MASK_OFF);  in mvebu_pcie_setup_hw()
250 	mvebu_writel(port, mask, PCIE_MASK_OFF);  in mvebu_pcie_setup_hw()
253 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,  in mvebu_pcie_hw_rd_conf()  argument
257 	mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),  in mvebu_pcie_hw_rd_conf()
260 	*val = mvebu_readl(port, PCIE_CONF_DATA_OFF);  in mvebu_pcie_hw_rd_conf()
270 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,  in mvebu_pcie_hw_wr_conf()  argument
276 	mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),  in mvebu_pcie_hw_wr_conf()
278 	_val = mvebu_readl(port, PCIE_CONF_DATA_OFF);  in mvebu_pcie_hw_wr_conf()
289 	mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);  in mvebu_pcie_hw_wr_conf()
298 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,  in mvebu_pcie_del_windows()  argument
316 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,  in mvebu_pcie_add_windows()  argument
332 			dev_err(&port->pcie->pdev->dev,  in mvebu_pcie_add_windows()
335 			mvebu_pcie_del_windows(port, base - size_mapped,  in mvebu_pcie_add_windows()
348 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)  in mvebu_pcie_handle_iobase_change()  argument
353 	if (port->bridge.iolimit < port->bridge.iobase ||  in mvebu_pcie_handle_iobase_change()
354 	    port->bridge.iolimitupper < port->bridge.iobaseupper ||  in mvebu_pcie_handle_iobase_change()
355 	    !(port->bridge.command & PCI_COMMAND_IO)) {  in mvebu_pcie_handle_iobase_change()
358 		if (port->iowin_base) {  in mvebu_pcie_handle_iobase_change()
359 			mvebu_pcie_del_windows(port, port->iowin_base,  in mvebu_pcie_handle_iobase_change()
360 					       port->iowin_size);  in mvebu_pcie_handle_iobase_change()
361 			port->iowin_base = 0;  in mvebu_pcie_handle_iobase_change()
362 			port->iowin_size = 0;  in mvebu_pcie_handle_iobase_change()
368 	if (!mvebu_has_ioport(port)) {  in mvebu_pcie_handle_iobase_change()
369 		dev_WARN(&port->pcie->pdev->dev,  in mvebu_pcie_handle_iobase_change()
381 	iobase = ((port->bridge.iobase & 0xF0) << 8) |  in mvebu_pcie_handle_iobase_change()
382 		(port->bridge.iobaseupper << 16);  in mvebu_pcie_handle_iobase_change()
383 	port->iowin_base = port->pcie->io.start + iobase;  in mvebu_pcie_handle_iobase_change()
384 	port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |  in mvebu_pcie_handle_iobase_change()
385 			    (port->bridge.iolimitupper << 16)) -  in mvebu_pcie_handle_iobase_change()
388 	mvebu_pcie_add_windows(port, port->io_target, port->io_attr,  in mvebu_pcie_handle_iobase_change()
389 			       port->iowin_base, port->iowin_size,  in mvebu_pcie_handle_iobase_change()
393 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)  in mvebu_pcie_handle_membase_change()  argument
396 	if (port->bridge.memlimit < port->bridge.membase ||  in mvebu_pcie_handle_membase_change()
397 	    !(port->bridge.command & PCI_COMMAND_MEMORY)) {  in mvebu_pcie_handle_membase_change()
400 		if (port->memwin_base) {  in mvebu_pcie_handle_membase_change()
401 			mvebu_pcie_del_windows(port, port->memwin_base,  in mvebu_pcie_handle_membase_change()
402 					       port->memwin_size);  in mvebu_pcie_handle_membase_change()
403 			port->memwin_base = 0;  in mvebu_pcie_handle_membase_change()
404 			port->memwin_size = 0;  in mvebu_pcie_handle_membase_change()
416 	port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);  in mvebu_pcie_handle_membase_change()
417 	port->memwin_size  =  in mvebu_pcie_handle_membase_change()
418 		(((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -  in mvebu_pcie_handle_membase_change()
419 		port->memwin_base + 1;  in mvebu_pcie_handle_membase_change()
421 	mvebu_pcie_add_windows(port, port->mem_target, port->mem_attr,  in mvebu_pcie_handle_membase_change()
422 			       port->memwin_base, port->memwin_size,  in mvebu_pcie_handle_membase_change()
430 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)  in mvebu_sw_pci_bridge_init()  argument
432 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_init()
438 	bridge->device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;  in mvebu_sw_pci_bridge_init()
439 	bridge->revision = mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;  in mvebu_sw_pci_bridge_init()
452 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,  in mvebu_sw_pci_bridge_read()  argument
455 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_read()
488 		if (!mvebu_has_ioport(port))  in mvebu_sw_pci_bridge_read()
531 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,  in mvebu_sw_pci_bridge_write()  argument
534 	struct mvebu_sw_pci_bridge *bridge = &port->bridge;  in mvebu_sw_pci_bridge_write()
547 	err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);  in mvebu_sw_pci_bridge_write()
558 		if (!mvebu_has_ioport(port))  in mvebu_sw_pci_bridge_write()
563 			mvebu_pcie_handle_iobase_change(port);  in mvebu_sw_pci_bridge_write()
565 			mvebu_pcie_handle_membase_change(port);  in mvebu_sw_pci_bridge_write()
581 		mvebu_pcie_handle_iobase_change(port);  in mvebu_sw_pci_bridge_write()
587 		mvebu_pcie_handle_membase_change(port);  in mvebu_sw_pci_bridge_write()
593 		mvebu_pcie_handle_iobase_change(port);  in mvebu_sw_pci_bridge_write()
601 		mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);  in mvebu_sw_pci_bridge_write()
623 		struct mvebu_pcie_port *port = &pcie->ports[i];  in mvebu_pcie_find_port()  local
625 		if (bus->number == 0 && port->devfn == devfn)  in mvebu_pcie_find_port()
626 			return port;  in mvebu_pcie_find_port()
628 		    bus->number >= port->bridge.secondary_bus &&  in mvebu_pcie_find_port()
629 		    bus->number <= port->bridge.subordinate_bus)  in mvebu_pcie_find_port()
630 			return port;  in mvebu_pcie_find_port()
641 	struct mvebu_pcie_port *port;  in mvebu_pcie_wr_conf()  local
644 	port = mvebu_pcie_find_port(pcie, bus, devfn);  in mvebu_pcie_wr_conf()
645 	if (!port)  in mvebu_pcie_wr_conf()
650 		return mvebu_sw_pci_bridge_write(port, where, size, val);  in mvebu_pcie_wr_conf()
652 	if (!mvebu_pcie_link_up(port))  in mvebu_pcie_wr_conf()
662 	if (bus->number == port->bridge.secondary_bus &&  in mvebu_pcie_wr_conf()
667 	ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,  in mvebu_pcie_wr_conf()
678 	struct mvebu_pcie_port *port;  in mvebu_pcie_rd_conf()  local
681 	port = mvebu_pcie_find_port(pcie, bus, devfn);  in mvebu_pcie_rd_conf()
682 	if (!port) {  in mvebu_pcie_rd_conf()
689 		return mvebu_sw_pci_bridge_read(port, where, size, val);  in mvebu_pcie_rd_conf()
691 	if (!mvebu_pcie_link_up(port)) {  in mvebu_pcie_rd_conf()
703 	if (bus->number == port->bridge.secondary_bus &&  in mvebu_pcie_rd_conf()
710 	ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,  in mvebu_pcie_rd_conf()
744 		struct mvebu_pcie_port *port = &pcie->ports[i];  in mvebu_pcie_setup()  local
746 		if (!port->base)  in mvebu_pcie_setup()
748 		mvebu_pcie_setup_hw(port);  in mvebu_pcie_setup()
827 					      struct mvebu_pcie_port *port)  in mvebu_pcie_map_registers()  argument
910 		struct mvebu_pcie_port *port = pcie->ports + i;  in mvebu_pcie_suspend()  local
911 		port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);  in mvebu_pcie_suspend()
924 		struct mvebu_pcie_port *port = pcie->ports + i;  in mvebu_pcie_resume()  local
925 		mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);  in mvebu_pcie_resume()
926 		mvebu_pcie_setup_hw(port);  in mvebu_pcie_resume()
988 		struct mvebu_pcie_port *port = &pcie->ports[i];  in mvebu_pcie_probe()  local
994 		port->pcie = pcie;  in mvebu_pcie_probe()
997 					 &port->port)) {  in mvebu_pcie_probe()
1004 					 &port->lane))  in mvebu_pcie_probe()
1005 			port->lane = 0;  in mvebu_pcie_probe()
1007 		port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",  in mvebu_pcie_probe()
1008 				       port->port, port->lane);  in mvebu_pcie_probe()
1010 		port->devfn = of_pci_get_devfn(child);  in mvebu_pcie_probe()
1011 		if (port->devfn < 0)  in mvebu_pcie_probe()
1014 		ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,  in mvebu_pcie_probe()
1015 					 &port->mem_target, &port->mem_attr);  in mvebu_pcie_probe()
1018 				port->port, port->lane);  in mvebu_pcie_probe()
1023 			mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,  in mvebu_pcie_probe()
1024 					   &port->io_target, &port->io_attr);  in mvebu_pcie_probe()
1026 			port->io_target = -1;  in mvebu_pcie_probe()
1027 			port->io_attr = -1;  in mvebu_pcie_probe()
1030 		port->reset_gpio = of_get_named_gpio_flags(child,  in mvebu_pcie_probe()
1032 		if (gpio_is_valid(port->reset_gpio)) {  in mvebu_pcie_probe()
1035 			port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;  in mvebu_pcie_probe()
1036 			port->reset_name = kasprintf(GFP_KERNEL,  in mvebu_pcie_probe()
1037 				     "pcie%d.%d-reset", port->port, port->lane);  in mvebu_pcie_probe()
1042 			    port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);  in mvebu_pcie_probe()
1049 			gpio_set_value(port->reset_gpio,  in mvebu_pcie_probe()
1050 				       (port->reset_active_low) ? 1 : 0);  in mvebu_pcie_probe()
1054 		port->clk = of_clk_get_by_name(child, NULL);  in mvebu_pcie_probe()
1055 		if (IS_ERR(port->clk)) {  in mvebu_pcie_probe()
1057 			       port->port, port->lane);  in mvebu_pcie_probe()
1061 		ret = clk_prepare_enable(port->clk);  in mvebu_pcie_probe()
1065 		port->base = mvebu_pcie_map_registers(pdev, child, port);  in mvebu_pcie_probe()
1066 		if (IS_ERR(port->base)) {  in mvebu_pcie_probe()
1068 				port->port, port->lane);  in mvebu_pcie_probe()
1069 			port->base = NULL;  in mvebu_pcie_probe()
1070 			clk_disable_unprepare(port->clk);  in mvebu_pcie_probe()
1074 		mvebu_pcie_set_local_dev_nr(port, 1);  in mvebu_pcie_probe()
1076 		port->dn = child;  in mvebu_pcie_probe()
1077 		mvebu_sw_pci_bridge_init(port);  in mvebu_pcie_probe()