131 		dev_dbg_f(zd_chip_dev(chip),  in zd_ioread32v_locked()
176 		dev_dbg_f(zd_chip_dev(chip),  in _zd_iowrite32v_async_locked()
221 			dev_dbg_f(zd_chip_dev(chip),  in zd_iowrite16a_locked()
258 			dev_dbg_f(zd_chip_dev(chip),  in zd_iowrite32a_locked()
339 	dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);  in read_pod()
356 	dev_dbg_f(zd_chip_dev(chip),  in read_pod()
390 		dev_dbg_f(zd_chip_dev(chip), "%s addr %pM\n", type, mac_addr);  in zd_write_mac_addr_common()
392 		dev_dbg_f(zd_chip_dev(chip), "set NULL %s\n", type);  in zd_write_mac_addr_common()
436 	dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);  in zd_read_regdomain()
572 	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);  in patch_cr157()
603 	dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);  in zd_chip_generic_patch_6m_band()
677 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd1211_hw_reset_phy()
759 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd1211b_hw_reset_phy()
786 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd1211_hw_init_hmac()
805 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd1211b_hw_init_hmac()
947 	dev_dbg_f(zd_chip_dev(chip), "\n");  in hw_init()
974 		dev_dbg_f(zd_chip_dev(chip),  in dump_cr()
979 	dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",  in dump_cr()
1012 		dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",  in dump_fw_registers()
1017 	dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);  in dump_fw_registers()
1018 	dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);  in dump_fw_registers()
1019 	dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);  in dump_fw_registers()
1020 	dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);  in dump_fw_registers()
1065 	dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);  in zd_chip_set_rts_cts_rate_locked()
1112 	dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",  in read_fw_regs_offset()
1121 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd_chip_read_mac_addr_fw()
1131 	dev_dbg_f(zd_chip_dev(chip), "\n");  in zd_chip_init_hw()
1270 	dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);  in patch_cck_gain()