Lines Matching refs:u8
230 u8 id; /* one of enum iw_mgmt_info_element_ids,
232 u8 len;
233 u8 data[0];
238 u8 essid[IW_ESSID_MAX_SIZE];
249 u8 data_rate_labels[IW_DATA_RATE_MAX_LABELS];
254 u8 chan;
259 u8 cfp_count;
260 u8 cfp_period;
272 u8 sync[16];
274 u8 signal;
275 u8 service;
280 u8 addr1[ETH_ALEN];
281 u8 addr2[ETH_ALEN];
282 u8 addr3[ETH_ALEN];
284 u8 addr4[ETH_ALEN];
290 u8 rx_blk_ctrl;
291 u8 rx_next_frame;
292 u8 rx_next_frame1;
293 u8 rssi;
295 u8 signal;
296 u8 service;
301 u8 addr1[ETH_ALEN];
302 u8 addr2[ETH_ALEN];
303 u8 addr3[ETH_ALEN];
305 u8 addr4[ETH_ALEN];
310 u8 sig_id;
311 u8 bss_type;
326 u8 sig_id;
327 u8 reserved;
331 u8 mac_addr[ETH_ALEN];
336 u8 sig_id;
337 u8 reserved;
343 u8 sig_id;
344 u8 mac_addr[ETH_ALEN];
349 u8 sig_id;
350 u8 reserved;
353 u8 mac_addr[ETH_ALEN];
358 u8 sig_id;
359 u8 reserved;
362 u8 mac_addr[ETH_ALEN];
367 u8 sig_id;
368 u8 reserved;
374 u8 sig_id;
375 u8 reserved;
378 u8 mib_value[100];
383 u8 sig_id;
384 u8 reserved;
389 u8 timestamp[8];
390 u8 local_time[8];
394 u8 bss_type;
395 u8 bssid[ETH_ALEN];
405 u8 sig_id;
406 u8 reserved;
412 u8 sig_id;
413 u8 pwr_save;
414 u8 wake_up;
415 u8 receive_dtims;
420 u8 sig_id;
421 u8 reserved;
427 u8 sig_id;
428 u8 bss_type;
432 u8 chan_list[14];
433 u8 bssid[ETH_ALEN];
440 u8 sig_id;
441 u8 reserved;
448 u8 bss_type;
449 u8 bssid[ETH_ALEN];
455 u8 rssi;
460 u8 sig_id;
461 u8 reserved;
467 u8 sig_id;
468 u8 routing;
471 u8 pri;
472 u8 service_class;
473 u8 daddr[ETH_ALEN];
474 u8 saddr[ETH_ALEN];
479 u8 sig_id;
480 u8 routing;
483 u8 reception;
484 u8 pri;
485 u8 service_class;
486 u8 daddr[ETH_ALEN];
487 u8 saddr[ETH_ALEN];
492 u8 sig_id;
493 u8 reserved;
495 u8 status;
496 u8 pri;
497 u8 service_class;
502 u8 sig_id;
507 #define WL3501_NIC_GCR ((u8)0x00) /* SIR0 - General Conf Register */
508 #define WL3501_NIC_BSS ((u8)0x01) /* SIR1 - Bank Switching Select Reg */
509 #define WL3501_NIC_LMAL ((u8)0x02) /* SIR2 - Local Mem addr Reg [7:0] */
510 #define WL3501_NIC_LMAH ((u8)0x03) /* SIR3 - Local Mem addr Reg [14:8] */
511 #define WL3501_NIC_IODPA ((u8)0x04) /* SIR4 - I/O Data Port A */
512 #define WL3501_NIC_IODPB ((u8)0x05) /* SIR5 - I/O Data Port B */
513 #define WL3501_NIC_IODPC ((u8)0x06) /* SIR6 - I/O Data Port C */
514 #define WL3501_NIC_IODPD ((u8)0x07) /* SIR7 - I/O Data Port D */
517 #define WL3501_GCR_SWRESET ((u8)0x80)
518 #define WL3501_GCR_CORESET ((u8)0x40)
519 #define WL3501_GCR_DISPWDN ((u8)0x20)
520 #define WL3501_GCR_ECWAIT ((u8)0x10)
521 #define WL3501_GCR_ECINT ((u8)0x08)
522 #define WL3501_GCR_INT2EC ((u8)0x04)
523 #define WL3501_GCR_ENECINT ((u8)0x02)
524 #define WL3501_GCR_DAM ((u8)0x01)
527 #define WL3501_BSS_FPAGE0 ((u8)0x20) /* Flash memory page0 */
528 #define WL3501_BSS_FPAGE1 ((u8)0x28)
529 #define WL3501_BSS_FPAGE2 ((u8)0x30)
530 #define WL3501_BSS_FPAGE3 ((u8)0x38)
531 #define WL3501_BSS_SPAGE0 ((u8)0x00) /* SRAM page0 */
532 #define WL3501_BSS_SPAGE1 ((u8)0x08)
533 #define WL3501_BSS_SPAGE2 ((u8)0x10)
534 #define WL3501_BSS_SPAGE3 ((u8)0x18)
541 u8 sync[16];
543 u8 signal;
544 u8 service;
576 u8 mac_addr[ETH_ALEN];
594 u8 bssid[ETH_ALEN];
599 u8 chan;
600 u8 cap_info;
604 u8 rssi;
605 u8 adhoc_times;
606 u8 reg_domain;
607 u8 version[2];