Lines Matching refs:u32
46 u32 PLCP_error;
51 u32 FCS_error;
56 u32 valid_frame;
60 u32 seq_num_miss;
89 u32 hw_version;
159 u32 tx_complete_timeout;
174 u32 rx_packet_ring_addr;
175 u32 tx_packet_ring_addr;
177 u32 rx_control_addr;
178 u32 tx_control_addr;
180 u32 tx_complete_addr;
197 u32 lifetime;
284 u32 config_options;
285 u32 filter_options;
331 u32 threshold;
513 u32 synch_fail_thold; /* number of beacons missed */
514 u32 bss_lose_timeout; /* number of TU's from synch fail */
577 u32 min_rate;
728 u32 event_mask;
729 u32 high_event_mask; /* Unused */
786 u32 options;
787 u32 data_flow_options;
807 u32 current_tsf_msb;
808 u32 current_tsf_lsb;
809 u32 last_TBTT_msb;
810 u32 last_TBTT_lsb;
869 u32 internal_desc_overflow;
873 u32 out_of_mem;
874 u32 hdr_overflow;
875 u32 hw_stuck;
876 u32 dropped;
877 u32 fcs_err;
878 u32 xfr_hint_trig;
879 u32 path_reset;
880 u32 reset_counter;
884 u32 rx_requested;
885 u32 rx_errors;
886 u32 tx_requested;
887 u32 tx_errors;
892 u32 cmd_cmplt;
895 u32 fiqs;
898 u32 rx_headers;
901 u32 rx_completes;
904 u32 rx_mem_overflow;
907 u32 rx_rdys;
910 u32 irqs;
913 u32 tx_procs;
916 u32 decrypt_done;
919 u32 dma0_done;
922 u32 dma1_done;
925 u32 tx_exch_complete;
928 u32 commands;
931 u32 rx_procs;
934 u32 hw_pm_mode_changes;
937 u32 host_acknowledges;
940 u32 pci_pm;
943 u32 wakeups;
946 u32 low_rssi;
951 u32 addr_key_count;
954 u32 default_key_count;
956 u32 reserved;
959 u32 key_not_found;
962 u32 decrypt_fail;
965 u32 packets;
968 u32 interrupt;
975 u32 ps_enter;
978 u32 elp_enter;
981 u32 missing_bcns;
984 u32 wake_on_host;
987 u32 wake_on_timer_exp;
990 u32 tx_with_ps;
993 u32 tx_without_ps;
996 u32 rcvd_beacons;
999 u32 power_save_off;
1014 u32 fix_tsf_ps;
1025 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
1028 u32 rcvd_awake_beacons;
1032 u32 rx_pkts;
1033 u32 calc_failure;
1037 u32 encrypt_fail;
1038 u32 decrypt_fail;
1039 u32 encrypt_packets;
1040 u32 decrypt_packets;
1041 u32 encrypt_interrupt;
1042 u32 decrypt_interrupt;
1046 u32 heart_beat;
1047 u32 calibration;
1048 u32 rx_mismatch;
1049 u32 rx_mem_empty;
1050 u32 rx_pool;
1051 u32 oom_late;
1052 u32 phy_transmit_error;
1053 u32 tx_stuck;
1057 u32 pspoll_timeouts;
1058 u32 upsd_timeouts;
1059 u32 upsd_max_sptime;
1060 u32 upsd_max_apturn;
1061 u32 pspoll_max_apturn;
1062 u32 pspoll_utilization;
1063 u32 upsd_utilization;
1067 u32 rx_prep_beacon_drop;
1068 u32 descr_host_int_trig_rx_data;
1069 u32 beacon_buffer_thres_host_int_trig_rx_data;
1070 u32 missed_beacon_host_int_trig_rx_data;
1071 u32 tx_xfr_host_int_trig_rx_data;
1095 u32 enabled_rates;
1105 u32 rate_class_cnt;
1187 u32 num_tx_mem_blocks;
1190 u32 num_rx_mem_blocks;
1327 u32 apsdconf[2];
1457 int wl1251_acx_feature_cfg(struct wl1251 *wl, u32 data_flow_options);
1462 int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time);
1463 int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter);
1467 void *mc_list, u32 mc_list_len);
1478 int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask);