Lines Matching refs:u8
226 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
227 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
229 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
230 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
231 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
232 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
233 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
234 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
238 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
240 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
241 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
242 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
243 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
244 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
814 u8 char_data;
817 u8 aifsn:4;
818 u8 acm:1;
819 u8 aci:2;
820 u8 reserved:1;
915 u8 *octet;
922 u8 addr1[ETH_ALEN];
923 u8 addr2[ETH_ALEN];
924 u8 addr3[ETH_ALEN];
926 u8 payload[0];
930 u8 id;
931 u8 len;
932 u8 data[0];
962 u8 aifs;
963 u8 flag;
992 u8 xaagccore1;
993 u8 xbagccore1;
994 u8 xcagccore1;
995 u8 xdagccore1;
996 u8 cca;
1020 u8 rx_rssi_percentage[4];
1021 u8 rx_evm_dbm[4];
1022 u8 rx_evm_percentage[2];
1032 u8 rate_adaptive_disabled;
1033 u8 ratr_state;
1038 u8 low2high_rssi_thresh_for_ra40m;
1040 u8 low2high_rssi_thresh_for_ra20m;
1050 u8 ping_rssi_enable;
1054 u8 pre_ratr_state;
1055 u8 ldpc_thres;
1068 u8 pricca_flag;
1069 u8 intf_flag;
1070 u8 intf_type;
1071 u8 dup_rts_flag;
1072 u8 monitor_flag;
1073 u8 ch_offset;
1074 u8 mf_state;
1120 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1122 u8 ctwindow;
1123 u8 opp_ps; /* opportunistic power save. */
1124 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1126 u8 noa_count_type[P2P_MAX_NOA_NUM];
1140 u8 offload_en:1;
1141 u8 role:1; /* 1: Owner, 0: Client */
1142 u8 ctwindow_en:1;
1143 u8 noa0_en:1;
1144 u8 noa1_en:1;
1145 u8 allstasleep:1;
1146 u8 discovery:1;
1147 u8 reserved:1;
1182 u8 rf_mode;
1183 u8 rf_type;
1184 u8 current_chan_bw;
1185 u8 set_bwmode_inprogress;
1186 u8 sw_chnl_inprogress;
1187 u8 sw_chnl_stage;
1188 u8 sw_chnl_step;
1189 u8 current_channel;
1190 u8 h2c_box_num;
1191 u8 set_io_inprogress;
1192 u8 lck_inprogress;
1203 u8 rfpienable;
1204 u8 reserve_0;
1213 u8 reg_837;
1221 u8 pwrgroup_cnt;
1222 u8 cck_high_power;
1231 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1234 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1237 u8 default_initialgain[4];
1240 u8 cur_cck_txpwridx;
1241 u8 cur_ofdm24g_txpwridx;
1242 u8 cur_bw20_txpwridx;
1243 u8 cur_bw40_txpwridx;
1262 u8 framesync;
1265 u8 num_total_rfpath;
1269 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1291 u8 agg_state;
1292 u8 rx_agg_state;
1307 u8 ratr_index;
1308 u8 wireless_mode;
1309 u8 mimo_ps;
1310 u8 mac_addr[ETH_ALEN];
1329 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1335 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1342 u8 mac_addr[ETH_ALEN];
1343 u8 mac80211_registered;
1344 u8 beacon_enabled;
1362 u8 p2p; /*using p2p role*/
1372 u8 cnt_after_linked;
1379 u8 ht_stbc_cap;
1380 u8 ht_cur_stbc;
1383 u8 vht_enable;
1384 u8 bw_80;
1385 u8 vht_cur_ldpc;
1386 u8 vht_cur_stbc;
1387 u8 vht_stbc_cap;
1388 u8 vht_ldpc_cap;
1394 u8 bssid[ETH_ALEN] __aligned(2);
1396 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1398 u8 ht_enable;
1399 u8 sgi_40;
1400 u8 sgi_20;
1401 u8 bw_40;
1403 u8 slot_time;
1404 u8 short_preamble;
1405 u8 use_cts_protect;
1406 u8 cur_40_prime_sc;
1407 u8 cur_40_prime_sc_bk;
1408 u8 cur_80_prime_sc;
1410 u8 retry_short;
1411 u8 retry_long;
1419 u8 min_space_cfg; /*For Min spacing configurations */
1420 u8 max_mss_density;
1421 u8 current_ampdu_factor;
1422 u8 current_ampdu_density;
1444 u8 tra_tdma_nav;
1445 u8 tra_tdma_ant;
1447 u8 tdma_ant;
1448 u8 tdma_nav;
1449 u8 tdma_dac_swing;
1450 u8 fw_dac_swing_lvl;
1452 u8 ps_tdma_byte[5];
1471 u8 c2h_bt_info;
1475 u8 bt_retry_cnt;
1476 u8 c2h_bt_info_original;
1477 u8 bt_inquiry_page_cnt;
1494 u8 ic_class;
1495 u8 oem_id;
1497 u8 state; /*stop 0, start 1 */
1498 u8 board_type;
1499 u8 external_pa;
1501 u8 pa_mode;
1502 u8 pa_type_2g;
1503 u8 pa_type_5g;
1504 u8 lna_type_2g;
1505 u8 lna_type_5g;
1506 u8 external_pa_2g;
1507 u8 external_lna_2g;
1508 u8 external_pa_5g;
1509 u8 external_lna_5g;
1510 u8 rfe_type;
1514 u8 *pfirmware;
1518 u8 last_hmeboxnum;
1521 u8 fw_rsvdpage_startoffset;
1522 u8 h2c_txcmd_seq;
1523 u8 current_ra_rate;
1529 u8 current_fwcmd_io;
1534 u8 fw_ps_state;
1539 u8 minspace_cfg; /*For Min spacing configurations */
1549 u8 macphyctl_reg;
1551 u8 max_earlymode_num;
1565 u8 rts_en;
1574 u8 *wowlan_firmware;
1576 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1594 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1597 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1598 u8 key_len[KEY_BUF_SIZE];
1602 u8 *pairwise_key;
1608 u8 bssid[6];
1609 u8 antsel_rx_keep_0;
1610 u8 antsel_rx_keep_1;
1611 u8 antsel_rx_keep_2;
1615 u8 fat_state;
1617 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1618 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1619 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1624 u8 rx_idle_ant;
1658 u8 txpowercount;
1659 u8 powerindex_backup[6];
1661 u8 thermalvalue_rxgain;
1662 u8 thermalvalue_iqk;
1663 u8 thermalvalue_lck;
1664 u8 thermalvalue;
1665 u8 last_dtp_lvl;
1666 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1667 u8 thermalvalue_avg_index;
1669 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1670 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1671 u8 dm_flag_tmp;
1672 u8 dm_type;
1673 u8 dm_rssi_sel;
1674 u8 txpower_track_control;
1678 u8 default_ofdm_index;
1679 u8 default_cck_index;
1700 u8 cfo_threshold;
1703 u8 tx_rate;
1706 u8 swing_idx_ofdm[MAX_RF_PATH];
1707 u8 swing_idx_ofdm_cur;
1708 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1710 u8 swing_idx_cck;
1711 u8 swing_idx_cck_cur;
1712 u8 swing_idx_cck_base;
1718 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1719 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1720 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1721 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1722 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1723 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1724 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1725 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1726 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1727 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1728 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1729 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1730 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1731 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1739 u8 resp_tx_path;
1740 u8 path_sel;
1746 u8 pre_channel;
1747 u8 *p_channel;
1748 u8 linked_interval;
1761 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1763 u8 efuse_usedpercentage;
1766 u8 efuse_re_pg_data[8];
1769 u8 autoload_failflag;
1770 u8 autoload_status;
1777 u8 eeprom_oemid;
1779 u8 eeprom_version;
1780 u8 board_type;
1781 u8 external_pa;
1783 u8 dev_addr[6];
1784 u8 wowlan_enable;
1785 u8 antenna_div_cfg;
1786 u8 antenna_div_type;
1789 u8 eeprom_crystalcap;
1790 u8 eeprom_tssi[2];
1791 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1792 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1793 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1794 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1795 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1796 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1798 u8 internal_pa_5g[2]; /* pathA / pathB */
1799 u8 eeprom_c9;
1800 u8 eeprom_cc;
1803 u8 eeprom_pwrgroup[2][3];
1804 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1805 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1807 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1809 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1811 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1832 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1833 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1839 u8 txpwr_safetyflag; /* Band edge enable flag */
1841 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1842 u8 antenna_txpwdiff[3];
1844 u8 eeprom_regulatory;
1845 u8 eeprom_thermalmeter;
1846 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1848 u8 crystalcap; /* CrystalCap. */
1849 u8 delta_iqk;
1850 u8 delta_lck;
1852 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1859 u8 channel_plan;
1881 u8 fwctrl_psmode;
1883 u8 reg_fwctrl_lps;
1886 u8 reg_max_lps_awakeintvl;
1900 u8 const_amdpci_aspm;
1924 u8 pwr_mode;
1925 u8 smart_ps;
1928 u8 wo_wlan_mode;
1929 u8 arp_offload_enable;
1930 u8 gtk_offload_enable;
1938 u8 psaddr[ETH_ALEN];
1941 u8 signal;
1942 u8 noise;
1943 u8 rate; /* hw desc rate */
1944 u8 received_channel;
1945 u8 control;
1946 u8 mask;
1947 u8 freq;
1951 u8 nic_type;
1953 u8 signalquality; /*in 0-100 index. */
1960 u8 signalstrength; /*in 0-100 index. */
1972 u8 rx_drvinfo_size;
1973 u8 rx_bufshift;
1977 u8 rx_packet_bw;
1979 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1981 u8 rx_mimo_evm_dbm[4];
1986 u8 rx_pwr[4]; /* per-path's pwdb */
1987 u8 rx_snr[4]; /* per-path's SNR */
1988 u8 bandwidth;
1989 u8 bt_coex_pwr_adjust;
1999 u8 vht_nss;
2001 u8 packet_report_type;
2004 u8 wake_match;
2033 u8 packet_bw:2;
2034 u8 multicast:1;
2035 u8 broadcast:1;
2037 u8 rts_stbc:1;
2038 u8 rts_enable:1;
2039 u8 cts_enable:1;
2040 u8 rts_use_shortpreamble:1;
2041 u8 rts_use_shortgi:1;
2042 u8 rts_sc:1;
2043 u8 rts_bw:1;
2044 u8 rts_rate;
2046 u8 use_shortgi:1;
2047 u8 use_shortpreamble:1;
2048 u8 use_driver_rate:1;
2049 u8 disable_ratefallback:1;
2051 u8 ratr_index;
2052 u8 mac_id;
2053 u8 hw_rate;
2055 u8 last_inipkt:1;
2056 u8 cmd_or_init:1;
2057 u8 queue_index;
2060 u8 empkt_num;
2069 u8 type;
2095 u8(*switch_channel) (struct ieee80211_hw *hw);
2101 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2102 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
2104 struct ieee80211_sta *sta, u8 rssi_level);
2105 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
2106 u8 *desc, u8 queue_index,
2108 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2110 u8 queue_index);
2111 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2112 u8 queue_index);
2114 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2115 u8 *pbd_desc_tx,
2118 struct sk_buff *skb, u8 hw_queue,
2120 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2122 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2128 u8 *pdesc, struct sk_buff *skb);
2130 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2132 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2137 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2138 u8 desc_name, u8 *val);
2139 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2141 u8 hw_queue, u16 index);
2142 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2145 u8 *macaddr, bool is_group, u8 enc_algo,
2162 u8 *powerlevel);
2164 u8 *ppowerlevel, u8 channel);
2166 u8 configtype);
2168 u8 configtype);
2176 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2177 u32 cmd_len, u8 *p_cmdbuffer);
2184 u8 index);
2185 u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
2190 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2268 u8 bar_id;
2369 u8 curcckpdstate_for_anothermacofdmsp;
2371 u8 curtxhighlvl_for_anothermacofdmsp;
2376 u8 pre_ccastate;
2377 u8 cur_ccasate;
2378 u8 pre_rfstate;
2379 u8 cur_rfstate;
2380 u8 initialize;
2396 u8 dig_enable_flag;
2397 u8 dig_ext_port_stage;
2398 u8 dig_algorithm;
2399 u8 dig_twoport_algorithm;
2400 u8 dig_dbgmode;
2401 u8 dig_slgorithm_switch;
2402 u8 cursta_cstate;
2403 u8 presta_cstate;
2404 u8 curmultista_cstate;
2405 u8 stop_dig;
2409 u8 rx_gain_max;
2410 u8 rx_gain_min;
2411 u8 min_undec_pwdb_for_dm;
2412 u8 rssi_val_min;
2413 u8 pre_cck_cca_thres;
2414 u8 cur_cck_cca_thres;
2415 u8 pre_cck_pd_state;
2416 u8 cur_cck_pd_state;
2417 u8 pre_cck_fa_state;
2418 u8 cur_cck_fa_state;
2419 u8 pre_ccastate;
2420 u8 cur_ccasate;
2421 u8 large_fa_hit;
2422 u8 forbidden_igi;
2423 u8 dig_state;
2424 u8 dig_highpwrstate;
2425 u8 cur_sta_cstate;
2426 u8 pre_sta_cstate;
2427 u8 cur_ap_cstate;
2428 u8 pre_ap_cstate;
2429 u8 cur_pd_thstate;
2430 u8 pre_pd_thstate;
2431 u8 cur_cs_ratiostate;
2432 u8 pre_cs_ratiostate;
2433 u8 backoff_enable_flag;
2436 u8 dig_min_0;
2437 u8 dig_min_1;
2438 u8 bt30_cur_igi;
2454 u8 bt_type;
2455 u8 btcoexist;
2456 u8 ant_num;
2463 u8 eeprom_bt_coexist;
2464 u8 eeprom_bt_type;
2465 u8 eeprom_bt_ant_num;
2466 u8 eeprom_bt_ant_isol;
2467 u8 eeprom_bt_radio_shared;
2469 u8 bt_coexistence;
2470 u8 bt_ant_num;
2471 u8 bt_coexist_type;
2472 u8 bt_state;
2473 u8 bt_cur_state; /* 0:on, 1:off */
2474 u8 bt_ant_isolation; /* 0:good, 1:bad */
2475 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2476 u8 bt_service;
2477 u8 bt_radio_shared_type;
2478 u8 bt_rfreg_origin_1e;
2479 u8 bt_rfreg_origin_1f;
2480 u8 bt_rssi_state;
2499 u8 bt_pre_rssi_state;
2500 u8 bt_pre_rssi_state1;
2502 u8 reg_bt_iso;
2503 u8 reg_bt_sco;
2505 u8 bt_active_zero_cnt;
2509 u8 bt_profile_case;
2510 u8 bt_profile_action;
2513 u8 lps_counter;
2520 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2521 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2522 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2523 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2529 u8 *tmp_buf, u8 length);
2534 u8 pkt_type);
2543 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2607 u8 rate_mask[5];
2630 u8 priv[0] __aligned(sizeof(void *));
2701 ((u8)(_val))
2709 EF1BYTE(*((u8 *)(_ptr)))
2718 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2760 (EF1BYTE(*((u8 *)(__pstart))))
2817 *((u8 *)(__pstart)) = EF1BYTE \
2820 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2866 (_os).octet = (u8 *)(_octet); \
2894 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) in rtl_read_byte()
2909 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8) in rtl_write_byte()
2983 static inline u8 get_rf_type(struct rtl_phy *rtlphy) in get_rf_type()
3010 const u8 *bssid) in get_sta()
3016 u8 *mac_addr) in rtl_find_sta()