Lines Matching refs:rtlphy
63 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_rf6052_set_cck_txpower() local
100 (rtlphy->mcs_txpwrlevel_origoffset[0][6]) + in rtl8821ae_phy_rf6052_set_cck_txpower()
101 (rtlphy->mcs_txpwrlevel_origoffset[0][7] << in rtl8821ae_phy_rf6052_set_cck_txpower()
105 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) + in rtl8821ae_phy_rf6052_set_cck_txpower()
106 (rtlphy->mcs_txpwrlevel_origoffset[0][15] << in rtl8821ae_phy_rf6052_set_cck_txpower()
150 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_get_power_base() local
166 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) in rtl8821ae_phy_get_power_base()
190 struct rtl_phy *rtlphy = &rtlpriv->phy; in get_txpower_writeval_by_regulatory() local
201 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index + in get_txpower_writeval_by_regulatory()
210 if (rtlphy->pwrgroup_cnt == 1) { in get_txpower_writeval_by_regulatory()
228 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup] in get_txpower_writeval_by_regulatory()
249 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { in get_txpower_writeval_by_regulatory()
265 else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) in get_txpower_writeval_by_regulatory()
269 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) in get_txpower_writeval_by_regulatory()
283 (u8)((rtlphy->mcs_txpwrlevel_origoffset in get_txpower_writeval_by_regulatory()
309 rtlphy->mcs_txpwrlevel_origoffset[chnlgroup] in get_txpower_writeval_by_regulatory()
408 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl8821ae_phy_rf6052_config() local
410 if (rtlphy->rf_type == RF_1T1R) in rtl8821ae_phy_rf6052_config()
411 rtlphy->num_total_rfpath = 1; in rtl8821ae_phy_rf6052_config()
413 rtlphy->num_total_rfpath = 2; in rtl8821ae_phy_rf6052_config()
421 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl8821ae_phy_rf6052_config_parafile() local
426 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { in _rtl8821ae_phy_rf6052_config_parafile()