Lines Matching refs:PWR_BASEADDR_MAC
48 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
51 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
54 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
67 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
70 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
82 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
85 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \
100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
106 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
132 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
135 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
141 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
147 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
158 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
160 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
162 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
165 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
168 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
171 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
189 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
192 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
198 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
212 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
215 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
245 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
251 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
254 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
257 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
260 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
263 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
266 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
272 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
275 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
278 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
281 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
284 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
295 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
298 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
304 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
313 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
319 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
397 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
401 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
405 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
408 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
414 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
417 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
420 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
426 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
429 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
432 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
435 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
438 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
445 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
448 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
451 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
454 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
457 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
460 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
463 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82 \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
471 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
474 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
478 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
481 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
484 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
488 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
492 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
497 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
501 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
504 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
507 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
510 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
521 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
530 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
533 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
538 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
542 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
545 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
548 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
551 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
562 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
571 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
574 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
577 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
580 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
585 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
589 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
592 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
595 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
600 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
605 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
608 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
611 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
614 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
617 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
620 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
623 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
626 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
629 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
632 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
635 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
638 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
641 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
649 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
652 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
655 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
658 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
661 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
667 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
670 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
673 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
676 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \