Lines Matching refs:PWR_BASEADDR_MAC
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
104 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
142 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
145 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
151 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
157 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
161 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
173 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
217 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
244 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
270 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
273 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
280 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
296 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
299 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
302 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
305 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
308 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
311 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
314 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
317 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
320 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
323 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
326 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
329 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
332 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
343 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
346 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
349 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
352 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
355 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
358 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
361 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
364 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
367 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
370 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},