Lines Matching refs:rtl_write_byte
288 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); in rtl92s_phy_set_bw_mode()
292 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode); in rtl92s_phy_set_bw_mode()
306 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58); in rtl92s_phy_set_bw_mode()
317 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18); in rtl92s_phy_set_bw_mode()
429 rtl_write_byte(rtlpriv, currentcmd->para1, in _rtl92s_phy_sw_chnl_step_by_step()
515 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp); in _rtl92se_phy_set_rf_sleep()
516 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0); in _rtl92se_phy_set_rf_sleep()
517 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF); in _rtl92se_phy_set_rf_sleep()
522 rtl_write_byte(rtlpriv, PHY_CCA, 0x0); in _rtl92se_phy_set_rf_sleep()
577 rtl_write_byte(rtlpriv, TXPAUSE, 0x00); in rtl92s_phy_set_rf_power_state()
578 rtl_write_byte(rtlpriv, PHY_CCA, 0x3); in rtl92s_phy_set_rf_power_state()
1046 rtl_write_byte(rtlpriv, ptraArray[i], (u8)ptraArray[i + 1]); in rtl92s_phy_mac_config()
1625 rtl_write_byte(rtlpriv, 0x554, 0x20); in rtl92s_phy_switch_ephy_parameter()
1629 rtl_write_byte(rtlpriv, 0x554, 0x3e); in rtl92s_phy_switch_ephy_parameter()
1633 rtl_write_byte(rtlpriv, 0x554, 0x39); in rtl92s_phy_switch_ephy_parameter()
1638 rtl_write_byte(rtlpriv, 0x560, 0x40); in rtl92s_phy_switch_ephy_parameter()
1640 rtl_write_byte(rtlpriv, 0x560, 0x00); in rtl92s_phy_switch_ephy_parameter()