123 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,  in _rtl92s_phy_rf_serial_read()
128 	rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);  in _rtl92s_phy_rf_serial_read()
131 	rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |  in _rtl92s_phy_rf_serial_read()
173 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);  in _rtl92s_phy_rf_serial_write()
302 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);  in rtl92s_phy_set_bw_mode()
303 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);  in rtl92s_phy_set_bw_mode()
309 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);  in rtl92s_phy_set_bw_mode()
310 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);  in rtl92s_phy_set_bw_mode()
312 		rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,  in rtl92s_phy_set_bw_mode()
314 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);  in rtl92s_phy_set_bw_mode()
1305 		rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1306 		rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1308 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);  in _rtl92s_phy_set_fwcmd_io()
1312 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);  in _rtl92s_phy_set_fwcmd_io()
1320 		rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1321 		rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);  in _rtl92s_phy_set_fwcmd_io()
1323 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);  in _rtl92s_phy_set_fwcmd_io()
1331 		rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);  in _rtl92s_phy_set_fwcmd_io()