Lines Matching refs:rtl_set_rfreg
317 rtl_set_rfreg(hw, rfpath, regaddr, RFREG_OFFSET_MASK, data); in _rtl92ee_config_rf_reg()
329 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
348 rtl_set_rfreg(hw, rfpath, regaddr, in _rtl92ee_config_rf_reg()
351 rtl_set_rfreg(hw, rfpath, 0x18, in _rtl92ee_config_rf_reg()
1922 rtl_set_rfreg(hw, (enum radio_path)rfpath, in _rtl92ee_phy_sw_chnl_step_by_step()
1972 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_iqk()
2013 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_iqk()
2059 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2060 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2061 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2062 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_a_rx_iqk()
2065 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2066 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2116 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2118 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2119 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2120 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_a_rx_iqk()
2123 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2124 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2155 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2175 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2176 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2177 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2178 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_b_rx_iqk()
2181 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2182 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2220 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2230 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2232 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2233 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2234 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_b_rx_iqk()
2237 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2238 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2269 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2441 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); in _rtl92ee_phy_path_a_standby()
2729 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2733 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2738 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl92ee_phy_lc_calibrate()
2744 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl92ee_phy_lc_calibrate()
2747 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
3078 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ee_phy_set_rf_sleep()