Lines Matching refs:rtl_set_bbreg
183 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92ee_phy_rf_serial_read()
186 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92ee_phy_rf_serial_read()
223 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92ee_phy_rf_serial_write()
271 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl92ee_phy_bb_config()
399 rtl_set_bbreg(hw, addr, MASKDWORD , data); in _rtl92ee_config_bb_reg()
762 rtl_set_bbreg(hw, array[i], MASKDWORD, in phy_config_bb_with_hdr_file()
790 rtl_set_bbreg(hw, in phy_config_bb_with_hdr_file()
1311 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1315 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE1, in _rtl92ee_set_txpower_index()
1319 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE2, in _rtl92ee_set_txpower_index()
1323 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE3, in _rtl92ee_set_txpower_index()
1327 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1331 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1335 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1339 rtl_set_bbreg(hw, RTXAGC_A_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1343 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1347 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1351 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1355 rtl_set_bbreg(hw, RTXAGC_A_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1359 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1363 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1367 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1371 rtl_set_bbreg(hw, RTXAGC_A_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1375 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1379 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1383 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1387 rtl_set_bbreg(hw, RTXAGC_A_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1391 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1395 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1399 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1403 rtl_set_bbreg(hw, RTXAGC_A_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1407 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1411 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1415 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1419 rtl_set_bbreg(hw, RTXAGC_A_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1430 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE1, in _rtl92ee_set_txpower_index()
1434 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE2, in _rtl92ee_set_txpower_index()
1438 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, MASKBYTE3, in _rtl92ee_set_txpower_index()
1442 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, in _rtl92ee_set_txpower_index()
1446 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE0, in _rtl92ee_set_txpower_index()
1450 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE1, in _rtl92ee_set_txpower_index()
1454 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE2, in _rtl92ee_set_txpower_index()
1458 rtl_set_bbreg(hw, RTXAGC_B_RATE18_06, MASKBYTE3, in _rtl92ee_set_txpower_index()
1462 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE0, in _rtl92ee_set_txpower_index()
1466 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE1, in _rtl92ee_set_txpower_index()
1470 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE2, in _rtl92ee_set_txpower_index()
1474 rtl_set_bbreg(hw, RTXAGC_B_RATE54_24, MASKBYTE3, in _rtl92ee_set_txpower_index()
1478 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE0, in _rtl92ee_set_txpower_index()
1482 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE1, in _rtl92ee_set_txpower_index()
1486 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE2, in _rtl92ee_set_txpower_index()
1490 rtl_set_bbreg(hw, RTXAGC_B_MCS03_MCS00, MASKBYTE3, in _rtl92ee_set_txpower_index()
1494 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE0, in _rtl92ee_set_txpower_index()
1498 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE1, in _rtl92ee_set_txpower_index()
1502 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE2, in _rtl92ee_set_txpower_index()
1506 rtl_set_bbreg(hw, RTXAGC_B_MCS07_MCS04, MASKBYTE3, in _rtl92ee_set_txpower_index()
1510 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE0, in _rtl92ee_set_txpower_index()
1514 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE1, in _rtl92ee_set_txpower_index()
1518 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE2, in _rtl92ee_set_txpower_index()
1522 rtl_set_bbreg(hw, RTXAGC_B_MCS11_MCS08, MASKBYTE3, in _rtl92ee_set_txpower_index()
1526 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE0, in _rtl92ee_set_txpower_index()
1530 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE1, in _rtl92ee_set_txpower_index()
1534 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE2, in _rtl92ee_set_txpower_index()
1538 rtl_set_bbreg(hw, RTXAGC_B_MCS15_MCS12, MASKBYTE3, in _rtl92ee_set_txpower_index()
1727 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1728 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1729 rtl_set_bbreg(hw, ROFDM0_TXPSEUDONOISEWGT, in rtl92ee_phy_set_bw_mode_callback()
1733 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1734 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1735 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND, in rtl92ee_phy_set_bw_mode_callback()
1737 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, in rtl92ee_phy_set_bw_mode_callback()
1740 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92ee_phy_set_bw_mode_callback()
1971 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1973 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1975 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1976 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1977 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1978 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1980 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1981 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1984 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1987 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1988 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
2012 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
2014 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
2016 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
2019 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2020 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2021 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
2022 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
2024 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
2025 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
2028 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
2031 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
2032 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
2057 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2069 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2072 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2073 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2076 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2077 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2078 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2079 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2081 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2082 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2085 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2088 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2089 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2104 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2111 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_a_rx_iqk()
2114 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2127 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2130 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2133 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2134 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2135 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2136 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2138 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2139 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2142 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2144 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2145 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2154 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2173 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2184 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2187 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2188 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2191 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2192 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2193 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2194 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2196 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2197 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2203 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2226 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp); in _rtl92ee_phy_path_b_rx_iqk()
2229 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2241 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2244 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2247 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2248 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2249 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2250 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2252 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2253 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2256 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2258 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2259 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2268 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2298 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2299 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2305 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2307 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2309 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29), in _rtl92ee_phy_path_a_fill_iqk_matrix()
2316 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2319 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2322 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2343 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2344 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2350 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2352 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2354 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25), in _rtl92ee_phy_path_b_fill_iqk_matrix()
2361 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2364 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2367 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2400 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]); in _rtl92ee_phy_reload_adda_registers()
2423 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2425 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl92ee_phy_path_adda_on()
2429 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon); in _rtl92ee_phy_path_adda_on()
2435 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); in _rtl92ee_phy_mac_setting_calibration()
2440 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2442 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2560 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92ee_phy_iq_calibrate()
2561 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2562 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2563 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2566 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); in _rtl92ee_phy_iq_calibrate()
2567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2568 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2574 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2575 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2576 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2628 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2629 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2630 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2679 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2696 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2697 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); in _rtl92ee_phy_iq_calibrate()
2699 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2700 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); in _rtl92ee_phy_iq_calibrate()
2704 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2705 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2768 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92ee_phy_set_rfpath_switch()
2772 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2775 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2778 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl92ee_phy_set_rfpath_switch()
2779 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl92ee_phy_set_rfpath_switch()
2786 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2788 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2791 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl92ee_phy_set_rfpath_switch()
2793 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2795 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in _rtl92ee_phy_set_rfpath_switch()
2798 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1); in _rtl92ee_phy_set_rfpath_switch()