176 	tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
180 		tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);  in _rtl92ee_phy_rf_serial_read()
189 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,  in _rtl92ee_phy_rf_serial_read()
192 		rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,  in _rtl92ee_phy_rf_serial_read()
195 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,  in _rtl92ee_phy_rf_serial_read()
198 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,  in _rtl92ee_phy_rf_serial_read()
673 	rtlphy->cck_high_power = (bool)(rtl_get_bbreg(hw,  in _rtl92ee_phy_bb8192ee_config_parafile()
1045 		(u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1047 		(u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1049 		(u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1051 		(u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);  in rtl92ee_phy_get_hw_reg_originalvalue()
1060 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,  in rtl92ee_phy_get_hw_reg_originalvalue()
1062 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,  in rtl92ee_phy_get_hw_reg_originalvalue()
1992 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1993 	reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
1994 	reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);  in _rtl92ee_phy_path_a_iqk()
2036 	reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2037 	reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2038 	reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);  in _rtl92ee_phy_path_b_iqk()
2094 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2095 	reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2096 	reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2149 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2150 	reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_a_rx_iqk()
2209 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2210 	reg_eb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2211 	reg_ebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2263 	reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2264 	reg_ec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2265 	reg_ecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD);  in _rtl92ee_phy_path_b_rx_iqk()
2292 		oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,  in _rtl92ee_phy_path_a_fill_iqk_matrix()
2337 		oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,  in _rtl92ee_phy_path_b_fill_iqk_matrix()
2378 		addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);  in _rtl92ee_phy_save_adda_registers()
2527 	u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0);  in _rtl92ee_phy_iq_calibrate()
2528 	u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0);  in _rtl92ee_phy_iq_calibrate()
2584 			result[t][0] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2588 			result[t][1] = (rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A,  in _rtl92ee_phy_iq_calibrate()
2604 			result[t][2] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2608 			result[t][3] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2637 				result[t][4] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2641 				result[t][5] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2657 				result[t][6] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()
2661 				result[t][7] = (rtl_get_bbreg(hw,  in _rtl92ee_phy_iq_calibrate()