1971 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_iqk()
1973 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_iqk()
2012 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_iqk()
2014 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_iqk()
2057 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2069 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2104 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2114 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2127 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_a_rx_iqk()
2154 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_a_rx_iqk()
2173 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2184 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2219 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2229 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2241 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_path_b_rx_iqk()
2268 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);  in _rtl92ee_phy_path_b_rx_iqk()
2574 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2628 		rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);  in _rtl92ee_phy_iq_calibrate()
2679 	rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0);  in _rtl92ee_phy_iq_calibrate()