177 	if (rfpath == RF90_PATH_A)  in _rtl92ee_phy_rf_serial_read()
188 	if (rfpath == RF90_PATH_A)  in _rtl92ee_phy_rf_serial_read()
369 	_rtl92ee_config_rf_reg(hw, addr, data, RF90_PATH_A,  in _rtl92ee_config_rf_radio_a()
507 	for (path = RF90_PATH_A; path <= RF90_PATH_B; ++path) {  in _rtl92ee_phy_store_txpower_by_rate_base()
508 		if (path == RF90_PATH_A) {  in _rtl92ee_phy_store_txpower_by_rate_base()
577 	for (rf = RF90_PATH_A; rf <= RF90_PATH_B; ++rf) {  in phy_convert_txpwr_dbm_to_rel_val()
578 		if (rf == RF90_PATH_A) {  in phy_convert_txpwr_dbm_to_rel_val()
939 	case RF90_PATH_A:  in rtl92ee_phy_config_rf_with_headerfile()
1075 	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in phy_init_bb_rf_register_def()
1078 	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1081 	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;  in phy_init_bb_rf_register_def()
1084 	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =  in phy_init_bb_rf_register_def()
1089 	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;  in phy_init_bb_rf_register_def()
1092 	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;  in phy_init_bb_rf_register_def()
1095 	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;  in phy_init_bb_rf_register_def()
1134 		if (path == RF90_PATH_A)  in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1308 	if (rfpath == RF90_PATH_A) {  in _rtl92ee_set_txpower_index()
1618 	for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;  in rtl92ee_phy_set_txpower_level()
1972 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_a_iqk()
2059 	rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);  in _rtl92ee_phy_path_a_rx_iqk()
2060 	rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);  in _rtl92ee_phy_path_a_rx_iqk()
2061 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);  in _rtl92ee_phy_path_a_rx_iqk()
2062 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);  in _rtl92ee_phy_path_a_rx_iqk()
2065 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);  in _rtl92ee_phy_path_a_rx_iqk()
2066 	rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);  in _rtl92ee_phy_path_a_rx_iqk()
2105 		rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_a_rx_iqk()
2116 	rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);  in _rtl92ee_phy_path_a_rx_iqk()
2118 	rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);  in _rtl92ee_phy_path_a_rx_iqk()
2119 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);  in _rtl92ee_phy_path_a_rx_iqk()
2120 	rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);  in _rtl92ee_phy_path_a_rx_iqk()
2123 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980);  in _rtl92ee_phy_path_a_rx_iqk()
2124 	rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000);  in _rtl92ee_phy_path_a_rx_iqk()
2155 	rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180);  in _rtl92ee_phy_path_a_rx_iqk()
2441 	rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000);  in _rtl92ee_phy_path_a_standby()
2723 		rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);  in _rtl92ee_phy_lc_calibrate()
2729 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,  in _rtl92ee_phy_lc_calibrate()
2736 	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);  in _rtl92ee_phy_lc_calibrate()
2738 	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);  in _rtl92ee_phy_lc_calibrate()
2744 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);  in _rtl92ee_phy_lc_calibrate()
3078 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);  in _rtl92ee_phy_set_rf_sleep()