Lines Matching refs:rtl_write_byte
394 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]); in rtl92d_phy_mac_config()
400 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); in rtl92d_phy_mac_config()
403 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); in rtl92d_phy_mac_config()
764 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); in rtl92d_phy_bb_config()
765 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); in rtl92d_phy_bb_config()
768 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | in rtl92d_phy_bb_config()
770 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA | in rtl92d_phy_bb_config()
772 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92d_phy_bb_config()
994 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); in rtl92d_phy_set_bw_mode()
998 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); in rtl92d_phy_set_bw_mode()
1002 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); in rtl92d_phy_set_bw_mode()
1095 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == in rtl92d_phy_switch_wirelessband()
1101 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex == in rtl92d_phy_switch_wirelessband()
1735 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]); in _rtl92d_phy_reload_mac_registers()
1736 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); in _rtl92d_phy_reload_mac_registers()
1762 rtl_write_byte(rtlpriv, macreg[0], 0x3F); in _rtl92d_phy_mac_setting_calibration()
1765 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & in _rtl92d_phy_mac_setting_calibration()
1767 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); in _rtl92d_phy_mac_setting_calibration()
2592 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92d_phy_lc_calibrate_sw()
2594 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_lc_calibrate_sw()
2668 rtl_write_byte(rtlpriv, offset, 0x50); in _rtl92d_phy_lc_calibrate_sw()
2669 rtl_write_byte(rtlpriv, offset, rf_mode[index]); in _rtl92d_phy_lc_calibrate_sw()
2672 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92d_phy_lc_calibrate_sw()
2674 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2831 rtl_write_byte(rtlpriv, currentcmd->para1, in _rtl92d_phy_sw_chnl_step_by_step()
3034 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92d_phy_set_rfon()
3036 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
3039 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfon()
3042 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfon()
3043 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
3045 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfon()
3055 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_set_rfsleep()
3059 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3067 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92d_phy_set_rfsleep()
3069 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3075 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfsleep()
3077 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3078 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfsleep()
3079 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfsleep()
3085 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3088 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92d_phy_set_rfsleep()
3219 rtl_write_byte(rtlpriv, offset, 0xF3); in rtl92d_phy_config_macphymode()
3224 rtl_write_byte(rtlpriv, offset, 0xF4); in rtl92d_phy_config_macphymode()
3229 rtl_write_byte(rtlpriv, offset, 0xF1); in rtl92d_phy_config_macphymode()
3325 rtl_write_byte(rtlpriv, mac_reg, value8); in rtl92d_phy_set_poweron()
3329 rtl_write_byte(rtlpriv, mac_reg, value8); in rtl92d_phy_set_poweron()
3334 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); in rtl92d_phy_set_poweron()
3339 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); in rtl92d_phy_set_poweron()
3342 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); in rtl92d_phy_set_poweron()
3369 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3370 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3374 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); in rtl92d_phy_config_maccoexist_rfpage()
3375 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3379 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3380 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); in rtl92d_phy_config_maccoexist_rfpage()
3585 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); in rtl92d_phy_check_poweroff()
3591 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON)); in rtl92d_phy_check_poweroff()
3596 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON)); in rtl92d_phy_check_poweroff()
3606 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); in rtl92d_phy_check_poweroff()