Lines Matching refs:rtl_set_bbreg
287 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
290 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); in _rtl92d_phy_rf_serial_read()
293 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, in _rtl92d_phy_rf_serial_read()
326 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); in _rtl92d_phy_rf_serial_write()
573 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, in _rtl92d_phy_config_bb_with_headerfile()
584 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
600 rtl_set_bbreg(hw, agctab_array_table[i], in _rtl92d_phy_config_bb_with_headerfile()
615 rtl_set_bbreg(hw, in _rtl92d_phy_config_bb_with_headerfile()
1011 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
1012 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
1014 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
1018 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
1019 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
1024 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, in rtl92d_phy_set_bw_mode()
1028 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
1030 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | in rtl92d_phy_set_bw_mode()
1032 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1050 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1051 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
1052 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
1085 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
1120 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1121 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1124 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
1127 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | in _rtl92d_phy_reload_imr_setting()
1136 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1137 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1); in _rtl92d_phy_reload_imr_setting()
1149 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1150 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
1159 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, in _rtl92d_phy_reload_imr_setting()
1161 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3); in _rtl92d_phy_reload_imr_setting()
1189 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in _rtl92d_phy_enable_rf_env()
1192 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in _rtl92d_phy_enable_rf_env()
1196 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1199 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1216 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); in _rtl92d_phy_restore_rf_env()
1220 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, in _rtl92d_phy_restore_rf_env()
1438 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1439 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1441 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1442 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1444 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1445 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1448 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1449 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1450 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1451 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1455 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1459 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1508 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1509 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1510 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1511 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1514 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1515 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1516 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1517 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1521 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1523 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1524 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1530 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1565 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1567 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_patha_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1583 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1625 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1626 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1627 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1628 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1631 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1632 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1633 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1634 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1638 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1641 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1642 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1649 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1683 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1685 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, in _rtl92d_phy_pathb_iqk_5g_normal()
1724 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); in _rtl92d_phy_reload_adda_registers()
1752 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); in _rtl92d_phy_path_adda_on()
1775 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1776 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1777 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1788 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1789 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1842 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1843 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1844 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1845 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1846 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1848 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1850 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, in _rtl92d_phy_iq_calibrate()
1857 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1859 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1862 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1863 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1864 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1929 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1949 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1950 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
2016 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
2017 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
2018 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
2019 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
2020 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
2023 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
2025 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
2028 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
2029 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
2030 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
2085 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2193 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
2194 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), in _rtl92d_phy_patha_fill_iqk_matrix()
2207 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
2209 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
2212 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), in _rtl92d_phy_patha_fill_iqk_matrix()
2222 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2224 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2226 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2251 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
2252 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), in _rtl92d_phy_pathb_fill_iqk_matrix()
2262 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2264 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2266 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), in _rtl92d_phy_pathb_fill_iqk_matrix()
2271 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2273 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2275 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2595 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2675 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
3400 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3401 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3403 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3404 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3407 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
3409 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
3411 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
3413 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3415 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3418 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3423 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3428 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3430 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3444 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, in rtl92d_update_bbrf_configuration()
3449 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
3455 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3456 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3458 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3459 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3462 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
3464 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
3466 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
3469 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3472 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3475 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3478 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD, in rtl92d_update_bbrf_configuration()
3481 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3484 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3486 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), in rtl92d_update_bbrf_configuration()
3489 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, in rtl92d_update_bbrf_configuration()
3494 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3496 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), in rtl92d_update_bbrf_configuration()
3498 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, in rtl92d_update_bbrf_configuration()
3505 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3506 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3507 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3508 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | in rtl92d_update_bbrf_configuration()
3510 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3511 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3512 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
3535 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
3536 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
3540 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | in rtl92d_update_bbrf_configuration()
3557 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
3558 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
3560 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()