Lines Matching refs:RFREG_OFFSET_MASK
367 if (bitmask != RFREG_OFFSET_MASK) { in rtl92d_phy_set_rf_reg()
827 RFREG_OFFSET_MASK, in rtl92d_phy_config_rf_with_headerfile()
834 RFREG_OFFSET_MASK, in rtl92d_phy_config_rf_with_headerfile()
1113 u32 rfmask = RFREG_OFFSET_MASK; in _rtl92d_phy_reload_imr_setting()
1156 RFREG_OFFSET_MASK, in _rtl92d_phy_reload_imr_setting()
1274 RFREG_OFFSET_MASK, 0xE439D); in _rtl92d_phy_switch_rf_setting()
1282 RFREG_OFFSET_MASK, u4tmp2); in _rtl92d_phy_switch_rf_setting()
1286 RFREG_OFFSET_MASK, in _rtl92d_phy_switch_rf_setting()
1296 RFREG_OFFSET_MASK)); in _rtl92d_phy_switch_rf_setting()
1326 RFREG_OFFSET_MASK, in _rtl92d_phy_switch_rf_setting()
1367 RFREG_OFFSET_MASK, in _rtl92d_phy_switch_rf_setting()
1373 RFREG_OFFSET_MASK, in _rtl92d_phy_switch_rf_setting()
1383 RFREG_OFFSET_MASK)); in _rtl92d_phy_switch_rf_setting()
1390 RFREG_OFFSET_MASK, in _rtl92d_phy_switch_rf_setting()
2602 RFREG_OFFSET_MASK, 0x010000); in _rtl92d_phy_lc_calibrate_sw()
2612 RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2617 RF_SYN_G6, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2621 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2641 RFREG_OFFSET_MASK, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2643 0x4F, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2857 RFREG_OFFSET_MASK, in _rtl92d_phy_sw_chnl_step_by_step()
3057 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3065 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3068 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3070 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3565 RF_CHNLBW, RFREG_OFFSET_MASK); in rtl92d_update_bbrf_configuration()
3567 RFREG_OFFSET_MASK); in rtl92d_update_bbrf_configuration()