299 	else if (rfpath == RF90_PATH_B)  in _rtl92d_phy_rf_serial_read()
417 	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
427 	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
437 	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
443 	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;  in _rtl92d_phy_init_bb_rf_register_definition()
449 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =  in _rtl92d_phy_init_bb_rf_register_definition()
455 	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
463 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
473 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;  in _rtl92d_phy_init_bb_rf_register_definition()
479 	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;  in _rtl92d_phy_init_bb_rf_register_definition()
484 	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
490 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
496 	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
502 	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
508 	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
514 	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
520 	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
526 	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
532 	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
831 	case RF90_PATH_B:  in rtl92d_phy_config_rf_with_headerfile()
893 		cckpowerlevel[RF90_PATH_B] =  in _rtl92d_get_txpower_index()
894 				 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];  in _rtl92d_get_txpower_index()
897 		cckpowerlevel[RF90_PATH_B] = 0;  in _rtl92d_get_txpower_index()
904 		ofdmpowerlevel[RF90_PATH_B] =  in _rtl92d_get_txpower_index()
905 		    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];  in _rtl92d_get_txpower_index()
910 		ofdmpowerlevel[RF90_PATH_B] =  in _rtl92d_get_txpower_index()
911 		    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];  in _rtl92d_get_txpower_index()
1182 	case RF90_PATH_B:  in _rtl92d_phy_enable_rf_env()
1218 	case RF90_PATH_B:  in _rtl92d_phy_restore_rf_env()
1233 	    BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;  in _rtl92d_phy_switch_rf_setting()
2523 		RF90_PATH_B : RF90_PATH_A;  in _rtl92d_phy_reload_lck_setting()