Lines Matching refs:rtlphy
101 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_rf_serial_read() local
102 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92c_phy_rf_serial_read()
155 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_rf_serial_write() local
156 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl92c_phy_rf_serial_write()
209 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_bb8192c_config_parafile() local
219 if (rtlphy->rf_type == RF_1T2R) { in _rtl92c_phy_bb8192c_config_parafile()
224 rtlphy->pwrgroup_cnt = 0; in _rtl92c_phy_bb8192c_config_parafile()
238 rtlphy->cck_high_power = in _rtl92c_phy_bb8192c_config_parafile()
251 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_store_pwrIndex_diffrate_offset() local
254 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = in _rtl92c_store_pwrIndex_diffrate_offset()
258 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
259 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
263 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] = in _rtl92c_store_pwrIndex_diffrate_offset()
267 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
268 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
272 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] = in _rtl92c_store_pwrIndex_diffrate_offset()
276 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
277 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
281 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] = in _rtl92c_store_pwrIndex_diffrate_offset()
285 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
286 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
290 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] = in _rtl92c_store_pwrIndex_diffrate_offset()
294 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
295 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
299 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] = in _rtl92c_store_pwrIndex_diffrate_offset()
303 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
304 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
308 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] = in _rtl92c_store_pwrIndex_diffrate_offset()
312 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
313 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
317 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] = in _rtl92c_store_pwrIndex_diffrate_offset()
321 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
322 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] = in _rtl92c_store_pwrIndex_diffrate_offset()
330 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
331 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] = in _rtl92c_store_pwrIndex_diffrate_offset()
339 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
340 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] = in _rtl92c_store_pwrIndex_diffrate_offset()
348 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
349 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] = in _rtl92c_store_pwrIndex_diffrate_offset()
357 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
358 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] = in _rtl92c_store_pwrIndex_diffrate_offset()
366 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
367 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] = in _rtl92c_store_pwrIndex_diffrate_offset()
375 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
376 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] = in _rtl92c_store_pwrIndex_diffrate_offset()
384 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
385 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] = in _rtl92c_store_pwrIndex_diffrate_offset()
393 rtlphy->pwrgroup_cnt, in _rtl92c_store_pwrIndex_diffrate_offset()
394 rtlphy->mcs_txpwrlevel_origoffset[rtlphy-> in _rtl92c_store_pwrIndex_diffrate_offset()
397 rtlphy->pwrgroup_cnt++; in _rtl92c_store_pwrIndex_diffrate_offset()
405 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_get_hw_reg_originalvalue() local
407 rtlphy->default_initialgain[0] = in rtl92c_phy_get_hw_reg_originalvalue()
409 rtlphy->default_initialgain[1] = in rtl92c_phy_get_hw_reg_originalvalue()
411 rtlphy->default_initialgain[2] = in rtl92c_phy_get_hw_reg_originalvalue()
413 rtlphy->default_initialgain[3] = in rtl92c_phy_get_hw_reg_originalvalue()
418 rtlphy->default_initialgain[0], in rtl92c_phy_get_hw_reg_originalvalue()
419 rtlphy->default_initialgain[1], in rtl92c_phy_get_hw_reg_originalvalue()
420 rtlphy->default_initialgain[2], in rtl92c_phy_get_hw_reg_originalvalue()
421 rtlphy->default_initialgain[3]); in rtl92c_phy_get_hw_reg_originalvalue()
423 rtlphy->framesync = (u8)rtl_get_bbreg(hw, in rtl92c_phy_get_hw_reg_originalvalue()
425 rtlphy->framesync_c34 = rtl_get_bbreg(hw, in rtl92c_phy_get_hw_reg_originalvalue()
430 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl92c_phy_get_hw_reg_originalvalue()
436 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_init_bb_rf_register_definition() local
438 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
439 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
440 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
441 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl92c_phy_init_bb_rf_register_definition()
443 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
444 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
445 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
446 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl92c_phy_init_bb_rf_register_definition()
448 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
449 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
451 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
452 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in _rtl92c_phy_init_bb_rf_register_definition()
454 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl92c_phy_init_bb_rf_register_definition()
456 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in _rtl92c_phy_init_bb_rf_register_definition()
459 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
460 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
461 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
462 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER; in _rtl92c_phy_init_bb_rf_register_definition()
464 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
465 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
466 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
467 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl92c_phy_init_bb_rf_register_definition()
469 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl92c_phy_init_bb_rf_register_definition()
470 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; in _rtl92c_phy_init_bb_rf_register_definition()
472 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl92c_phy_init_bb_rf_register_definition()
473 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in _rtl92c_phy_init_bb_rf_register_definition()
475 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
476 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
477 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
478 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; in _rtl92c_phy_init_bb_rf_register_definition()
480 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
481 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
482 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
483 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl92c_phy_init_bb_rf_register_definition()
485 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
486 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
487 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
488 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl92c_phy_init_bb_rf_register_definition()
490 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
491 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
492 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; in _rtl92c_phy_init_bb_rf_register_definition()
493 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
495 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
496 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
497 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
498 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
500 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
501 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
502 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
503 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in _rtl92c_phy_init_bb_rf_register_definition()
505 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
506 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
507 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
508 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; in _rtl92c_phy_init_bb_rf_register_definition()
510 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
511 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
512 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
513 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; in _rtl92c_phy_init_bb_rf_register_definition()
515 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; in _rtl92c_phy_init_bb_rf_register_definition()
516 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; in _rtl92c_phy_init_bb_rf_register_definition()
524 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_get_txpower_level() local
529 txpwr_level = rtlphy->cur_cck_txpwridx; in rtl92c_phy_get_txpower_level()
532 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + in rtl92c_phy_get_txpower_level()
539 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl92c_phy_get_txpower_level()
552 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_get_txpower_index() local
560 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) { in _rtl92c_get_txpower_index()
565 } else if (get_rf_type(rtlphy) == RF_2T2R) { in _rtl92c_get_txpower_index()
578 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_ccxpower_index_check() local
580 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92c_ccxpower_index_check()
581 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92c_ccxpower_index_check()
605 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_update_txpower_dbm() local
629 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92c_phy_update_txpower_dbm()
694 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_bw_mode() local
696 u8 tmp_bw = rtlphy->current_chan_bw; in rtl92c_phy_set_bw_mode()
698 if (rtlphy->set_bwmode_inprogress) in rtl92c_phy_set_bw_mode()
700 rtlphy->set_bwmode_inprogress = true; in rtl92c_phy_set_bw_mode()
706 rtlphy->set_bwmode_inprogress = false; in rtl92c_phy_set_bw_mode()
707 rtlphy->current_chan_bw = tmp_bw; in rtl92c_phy_set_bw_mode()
716 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_sw_chnl_callback() local
720 "switch to channel%d\n", rtlphy->current_channel); in rtl92c_phy_sw_chnl_callback()
724 if (!rtlphy->sw_chnl_inprogress) in rtl92c_phy_sw_chnl_callback()
727 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, in rtl92c_phy_sw_chnl_callback()
728 &rtlphy->sw_chnl_step, &delay)) { in rtl92c_phy_sw_chnl_callback()
734 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl_callback()
745 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_sw_chnl() local
748 if (rtlphy->sw_chnl_inprogress) in rtl92c_phy_sw_chnl()
750 if (rtlphy->set_bwmode_inprogress) in rtl92c_phy_sw_chnl()
752 RT_ASSERT((rtlphy->current_channel <= 14), in rtl92c_phy_sw_chnl()
754 rtlphy->sw_chnl_inprogress = true; in rtl92c_phy_sw_chnl()
755 rtlphy->sw_chnl_stage = 0; in rtl92c_phy_sw_chnl()
756 rtlphy->sw_chnl_step = 0; in rtl92c_phy_sw_chnl()
761 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl()
765 rtlphy->sw_chnl_inprogress = false; in rtl92c_phy_sw_chnl()
774 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_sw_rf_seting() local
778 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { in _rtl92c_phy_sw_rf_seting()
819 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_sw_chnl_step_by_step() local
828 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl92c_phy_sw_chnl_step_by_step()
900 rtlphy->rfreg_chnlval[rfpath] = in _rtl92c_phy_sw_chnl_step_by_step()
901 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl92c_phy_sw_chnl_step_by_step()
907 rtlphy->rfreg_chnlval[rfpath]); in _rtl92c_phy_sw_chnl_step_by_step()
1234 struct rtl_phy *rtlphy = &(rtlpriv->phy); in _rtl92c_phy_iq_calibrate() local
1253 rtlphy->adda_backup, 16); in _rtl92c_phy_iq_calibrate()
1255 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1259 rtlphy->rfpi_enable = in _rtl92c_phy_iq_calibrate()
1264 if (!rtlphy->rfpi_enable) in _rtl92c_phy_iq_calibrate()
1267 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1268 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1269 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1279 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1338 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl92c_phy_iq_calibrate()
1339 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl92c_phy_iq_calibrate()
1340 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl92c_phy_iq_calibrate()
1346 if (!rtlphy->rfpi_enable) in _rtl92c_phy_iq_calibrate()
1349 rtlphy->adda_backup, 16); in _rtl92c_phy_iq_calibrate()
1351 rtlphy->iqk_mac_backup); in _rtl92c_phy_iq_calibrate()
1390 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_iq_calibrate() local
1415 rtlphy->iqk_bb_backup, 10); in rtl92c_phy_iq_calibrate()
1479 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; in rtl92c_phy_iq_calibrate()
1480 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; in rtl92c_phy_iq_calibrate()
1483 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; in rtl92c_phy_iq_calibrate()
1484 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; in rtl92c_phy_iq_calibrate()
1490 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; in rtl92c_phy_iq_calibrate()
1491 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; in rtl92c_phy_iq_calibrate()
1505 rtlphy->iqk_bb_backup, 10); in rtl92c_phy_iq_calibrate()
1524 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_ap_calibrate() local
1527 if (rtlphy->apk_done) in rtl92c_phy_ap_calibrate()
1550 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_io_cmd() local
1555 iotype, rtlphy->set_io_inprogress); in rtl92c_phy_set_io_cmd()
1574 if (postprocessing && !rtlphy->set_io_inprogress) { in rtl92c_phy_set_io_cmd()
1575 rtlphy->set_io_inprogress = true; in rtl92c_phy_set_io_cmd()
1576 rtlphy->current_io_type = iotype; in rtl92c_phy_set_io_cmd()
1589 struct rtl_phy *rtlphy = &(rtlpriv->phy); in rtl92c_phy_set_io() local
1594 rtlphy->current_io_type, rtlphy->set_io_inprogress); in rtl92c_phy_set_io()
1595 switch (rtlphy->current_io_type) { in rtl92c_phy_set_io()
1597 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; in rtl92c_phy_set_io()
1599 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl92c_phy_set_io()
1602 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; in rtl92c_phy_set_io()
1611 rtlphy->set_io_inprogress = false; in rtl92c_phy_set_io()
1613 "(%#x)\n", rtlphy->current_io_type); in rtl92c_phy_set_io()