Lines Matching refs:PWR_BASEADDR_MAC
68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
86 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
89 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
97 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
100 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
103 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4) \
119 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \
123 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
144 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
149 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
153 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) \
157 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
164 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
186 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \
188 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
193 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
200 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
203 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
206 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
209 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
212 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0 \
215 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F \
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0 \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5) \
233 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
236 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
239 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
242 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
245 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \
248 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \
251 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
257 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0) \
260 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \