Lines Matching refs:rtlphy
169 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_rf_serial_read() local
170 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl88e_phy_rf_serial_read()
219 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_rf_serial_write() local
220 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; in _rtl88e_phy_rf_serial_write()
370 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_bb8188e_config_parafile() local
381 rtlphy->pwrgroup_cnt = 0; in _rtl88e_phy_bb8188e_config_parafile()
395 rtlphy->cck_high_power = in _rtl88e_phy_bb8188e_config_parafile()
543 struct rtl_phy *rtlphy = &rtlpriv->phy; in store_pwrindex_rate_offset() local
544 int count = rtlphy->pwrgroup_cnt; in store_pwrindex_rate_offset()
547 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data; in store_pwrindex_rate_offset()
551 rtlphy->mcs_txpwrlevel_origoffset[count][0]); in store_pwrindex_rate_offset()
554 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data; in store_pwrindex_rate_offset()
558 rtlphy->mcs_txpwrlevel_origoffset[count][1]); in store_pwrindex_rate_offset()
561 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data; in store_pwrindex_rate_offset()
565 rtlphy->mcs_txpwrlevel_origoffset[count][6]); in store_pwrindex_rate_offset()
568 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data; in store_pwrindex_rate_offset()
572 rtlphy->mcs_txpwrlevel_origoffset[count][7]); in store_pwrindex_rate_offset()
575 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data; in store_pwrindex_rate_offset()
579 rtlphy->mcs_txpwrlevel_origoffset[count][2]); in store_pwrindex_rate_offset()
582 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data; in store_pwrindex_rate_offset()
586 rtlphy->mcs_txpwrlevel_origoffset[count][3]); in store_pwrindex_rate_offset()
589 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data; in store_pwrindex_rate_offset()
593 rtlphy->mcs_txpwrlevel_origoffset[count][4]); in store_pwrindex_rate_offset()
596 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data; in store_pwrindex_rate_offset()
597 if (get_rf_type(rtlphy) == RF_1T1R) { in store_pwrindex_rate_offset()
599 rtlphy->pwrgroup_cnt = count; in store_pwrindex_rate_offset()
604 rtlphy->mcs_txpwrlevel_origoffset[count][5]); in store_pwrindex_rate_offset()
607 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data; in store_pwrindex_rate_offset()
611 rtlphy->mcs_txpwrlevel_origoffset[count][8]); in store_pwrindex_rate_offset()
614 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data; in store_pwrindex_rate_offset()
618 rtlphy->mcs_txpwrlevel_origoffset[count][9]); in store_pwrindex_rate_offset()
621 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data; in store_pwrindex_rate_offset()
625 rtlphy->mcs_txpwrlevel_origoffset[count][14]); in store_pwrindex_rate_offset()
628 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data; in store_pwrindex_rate_offset()
632 rtlphy->mcs_txpwrlevel_origoffset[count][15]); in store_pwrindex_rate_offset()
635 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data; in store_pwrindex_rate_offset()
639 rtlphy->mcs_txpwrlevel_origoffset[count][10]); in store_pwrindex_rate_offset()
642 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data; in store_pwrindex_rate_offset()
646 rtlphy->mcs_txpwrlevel_origoffset[count][11]); in store_pwrindex_rate_offset()
649 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data; in store_pwrindex_rate_offset()
653 rtlphy->mcs_txpwrlevel_origoffset[count][12]); in store_pwrindex_rate_offset()
656 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data; in store_pwrindex_rate_offset()
660 rtlphy->mcs_txpwrlevel_origoffset[count][13]); in store_pwrindex_rate_offset()
661 if (get_rf_type(rtlphy) != RF_1T1R) { in store_pwrindex_rate_offset()
663 rtlphy->pwrgroup_cnt = count; in store_pwrindex_rate_offset()
819 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_get_hw_reg_originalvalue() local
821 rtlphy->default_initialgain[0] = in rtl88e_phy_get_hw_reg_originalvalue()
823 rtlphy->default_initialgain[1] = in rtl88e_phy_get_hw_reg_originalvalue()
825 rtlphy->default_initialgain[2] = in rtl88e_phy_get_hw_reg_originalvalue()
827 rtlphy->default_initialgain[3] = in rtl88e_phy_get_hw_reg_originalvalue()
832 rtlphy->default_initialgain[0], in rtl88e_phy_get_hw_reg_originalvalue()
833 rtlphy->default_initialgain[1], in rtl88e_phy_get_hw_reg_originalvalue()
834 rtlphy->default_initialgain[2], in rtl88e_phy_get_hw_reg_originalvalue()
835 rtlphy->default_initialgain[3]); in rtl88e_phy_get_hw_reg_originalvalue()
837 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, in rtl88e_phy_get_hw_reg_originalvalue()
839 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, in rtl88e_phy_get_hw_reg_originalvalue()
844 ROFDM0_RXDETECTOR3, rtlphy->framesync); in rtl88e_phy_get_hw_reg_originalvalue()
850 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_init_bb_rf_register_definition() local
852 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()
853 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()
854 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()
855 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()
857 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()
858 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()
859 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()
860 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()
862 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
863 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
865 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
866 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
868 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl88e_phy_init_bb_rf_register_definition()
870 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = in _rtl88e_phy_init_bb_rf_register_definition()
873 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()
874 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()
875 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()
876 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()
878 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
879 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
880 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
881 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
883 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl88e_phy_init_bb_rf_register_definition()
884 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; in _rtl88e_phy_init_bb_rf_register_definition()
886 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl88e_phy_init_bb_rf_register_definition()
887 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; in _rtl88e_phy_init_bb_rf_register_definition()
889 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()
891 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()
893 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()
895 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()
898 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()
899 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()
900 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()
901 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()
903 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()
904 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()
905 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()
906 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()
908 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
909 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
910 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE; in _rtl88e_phy_init_bb_rf_register_definition()
911 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
913 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
914 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
915 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
916 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
918 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
919 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
920 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
921 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
923 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
924 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
926 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl88e_phy_init_bb_rf_register_definition()
927 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; in _rtl88e_phy_init_bb_rf_register_definition()
929 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; in _rtl88e_phy_init_bb_rf_register_definition()
930 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK; in _rtl88e_phy_init_bb_rf_register_definition()
936 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_get_txpower_level() local
940 txpwr_level = rtlphy->cur_cck_txpwridx; in rtl88e_phy_get_txpower_level()
943 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl88e_phy_get_txpower_level()
950 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; in rtl88e_phy_get_txpower_level()
1022 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_ccxpower_index_check() local
1024 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl88e_ccxpower_index_check()
1025 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl88e_ccxpower_index_check()
1026 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0]; in _rtl88e_ccxpower_index_check()
1027 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0]; in _rtl88e_ccxpower_index_check()
1109 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_set_bw_mode_callback() local
1116 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? in rtl88e_phy_set_bw_mode_callback()
1120 rtlphy->set_bwmode_inprogress = false; in rtl88e_phy_set_bw_mode_callback()
1127 switch (rtlphy->current_chan_bw) { in rtl88e_phy_set_bw_mode_callback()
1141 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); in rtl88e_phy_set_bw_mode_callback()
1145 switch (rtlphy->current_chan_bw) { in rtl88e_phy_set_bw_mode_callback()
1166 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw); in rtl88e_phy_set_bw_mode_callback()
1169 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); in rtl88e_phy_set_bw_mode_callback()
1170 rtlphy->set_bwmode_inprogress = false; in rtl88e_phy_set_bw_mode_callback()
1178 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_set_bw_mode() local
1180 u8 tmp_bw = rtlphy->current_chan_bw; in rtl88e_phy_set_bw_mode()
1182 if (rtlphy->set_bwmode_inprogress) in rtl88e_phy_set_bw_mode()
1184 rtlphy->set_bwmode_inprogress = true; in rtl88e_phy_set_bw_mode()
1190 rtlphy->set_bwmode_inprogress = false; in rtl88e_phy_set_bw_mode()
1191 rtlphy->current_chan_bw = tmp_bw; in rtl88e_phy_set_bw_mode()
1199 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_sw_chnl_callback() local
1203 "switch to channel%d\n", rtlphy->current_channel); in rtl88e_phy_sw_chnl_callback()
1207 if (!rtlphy->sw_chnl_inprogress) in rtl88e_phy_sw_chnl_callback()
1210 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage, in rtl88e_phy_sw_chnl_callback()
1211 &rtlphy->sw_chnl_step, &delay)) { in rtl88e_phy_sw_chnl_callback()
1217 rtlphy->sw_chnl_inprogress = false; in rtl88e_phy_sw_chnl_callback()
1227 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_sw_chnl() local
1230 if (rtlphy->sw_chnl_inprogress) in rtl88e_phy_sw_chnl()
1232 if (rtlphy->set_bwmode_inprogress) in rtl88e_phy_sw_chnl()
1234 RT_ASSERT((rtlphy->current_channel <= 14), in rtl88e_phy_sw_chnl()
1236 rtlphy->sw_chnl_inprogress = true; in rtl88e_phy_sw_chnl()
1237 rtlphy->sw_chnl_stage = 0; in rtl88e_phy_sw_chnl()
1238 rtlphy->sw_chnl_step = 0; in rtl88e_phy_sw_chnl()
1243 rtlphy->current_channel); in rtl88e_phy_sw_chnl()
1244 rtlphy->sw_chnl_inprogress = false; in rtl88e_phy_sw_chnl()
1248 rtlphy->sw_chnl_inprogress = false; in rtl88e_phy_sw_chnl()
1258 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_sw_chnl_step_by_step() local
1267 u8 num_total_rfpath = rtlphy->num_total_rfpath; in _rtl88e_phy_sw_chnl_step_by_step()
1337 rtlphy->rfreg_chnlval[rfpath] = in _rtl88e_phy_sw_chnl_step_by_step()
1338 ((rtlphy->rfreg_chnlval[rfpath] & in _rtl88e_phy_sw_chnl_step_by_step()
1344 rtlphy->rfreg_chnlval[rfpath]); in _rtl88e_phy_sw_chnl_step_by_step()
1718 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl88e_phy_iq_calibrate() local
1739 rtlphy->adda_backup, 16); in _rtl88e_phy_iq_calibrate()
1741 rtlphy->iqk_mac_backup); in _rtl88e_phy_iq_calibrate()
1743 rtlphy->iqk_bb_backup, in _rtl88e_phy_iq_calibrate()
1748 rtlphy->rfpi_enable = in _rtl88e_phy_iq_calibrate()
1752 if (!rtlphy->rfpi_enable) in _rtl88e_phy_iq_calibrate()
1770 rtlphy->iqk_mac_backup); in _rtl88e_phy_iq_calibrate()
1844 if (!rtlphy->rfpi_enable) in _rtl88e_phy_iq_calibrate()
1847 rtlphy->adda_backup, 16); in _rtl88e_phy_iq_calibrate()
1849 rtlphy->iqk_mac_backup); in _rtl88e_phy_iq_calibrate()
1851 rtlphy->iqk_bb_backup, in _rtl88e_phy_iq_calibrate()
1963 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_iq_calibrate() local
1985 rtlphy->iqk_bb_backup, 9); in rtl88e_phy_iq_calibrate()
2002 if (get_rf_type(rtlphy) == RF_2T2R) in rtl88e_phy_iq_calibrate()
2055 rtlphy->reg_eb4 = reg_eb4; in rtl88e_phy_iq_calibrate()
2056 rtlphy->reg_ebc = reg_ebc; in rtl88e_phy_iq_calibrate()
2057 rtlphy->reg_e94 = reg_e94; in rtl88e_phy_iq_calibrate()
2058 rtlphy->reg_e9c = reg_e9c; in rtl88e_phy_iq_calibrate()
2062 rtlphy->reg_e94 = 0x100; in rtl88e_phy_iq_calibrate()
2063 rtlphy->reg_eb4 = 0x100; in rtl88e_phy_iq_calibrate()
2064 rtlphy->reg_e9c = 0x0; in rtl88e_phy_iq_calibrate()
2065 rtlphy->reg_ebc = 0x0; in rtl88e_phy_iq_calibrate()
2073 rtlphy->iqk_matrix[0].value[0][i] = in rtl88e_phy_iq_calibrate()
2075 rtlphy->iqk_matrix[0].iqk_done = true; in rtl88e_phy_iq_calibrate()
2079 rtlphy->iqk_bb_backup, 9); in rtl88e_phy_iq_calibrate()
2085 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_lc_calibrate() local
2094 rtlphy->lck_inprogress = true; in rtl88e_phy_lc_calibrate()
2101 rtlphy->lck_inprogress = false; in rtl88e_phy_lc_calibrate()
2112 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_set_io_cmd() local
2117 iotype, rtlphy->set_io_inprogress); in rtl88e_phy_set_io_cmd()
2136 if (postprocessing && !rtlphy->set_io_inprogress) { in rtl88e_phy_set_io_cmd()
2137 rtlphy->set_io_inprogress = true; in rtl88e_phy_set_io_cmd()
2138 rtlphy->current_io_type = iotype; in rtl88e_phy_set_io_cmd()
2150 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl88e_phy_set_io() local
2155 rtlphy->current_io_type, rtlphy->set_io_inprogress); in rtl88e_phy_set_io()
2156 switch (rtlphy->current_io_type) { in rtl88e_phy_set_io()
2158 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; in rtl88e_phy_set_io()
2160 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel); in rtl88e_phy_set_io()
2164 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue; in rtl88e_phy_set_io()
2173 rtlphy->set_io_inprogress = false; in rtl88e_phy_set_io()
2175 "(%#x)\n", rtlphy->current_io_type); in rtl88e_phy_set_io()