Lines Matching refs:RF90_PATH_A
183 if (rfpath == RF90_PATH_A) in _rtl88e_phy_rf_serial_read()
194 if (rfpath == RF90_PATH_A) in _rtl88e_phy_rf_serial_read()
342 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A, in _rtl8188e_config_rf_radio_a()
805 case RF90_PATH_A: in rtl88e_phy_config_rf_with_headerfile()
852 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; in _rtl88e_phy_init_bb_rf_register_definition()
857 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; in _rtl88e_phy_init_bb_rf_register_definition()
862 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
865 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; in _rtl88e_phy_init_bb_rf_register_definition()
868 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = in _rtl88e_phy_init_bb_rf_register_definition()
873 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; in _rtl88e_phy_init_bb_rf_register_definition()
878 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; in _rtl88e_phy_init_bb_rf_register_definition()
883 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; in _rtl88e_phy_init_bb_rf_register_definition()
886 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; in _rtl88e_phy_init_bb_rf_register_definition()
889 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = in _rtl88e_phy_init_bb_rf_register_definition()
898 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; in _rtl88e_phy_init_bb_rf_register_definition()
903 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; in _rtl88e_phy_init_bb_rf_register_definition()
908 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
913 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
918 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; in _rtl88e_phy_init_bb_rf_register_definition()
923 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; in _rtl88e_phy_init_bb_rf_register_definition()
926 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; in _rtl88e_phy_init_bb_rf_register_definition()
929 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK; in _rtl88e_phy_init_bb_rf_register_definition()
964 cckpowerlevel[RF90_PATH_A] = in handle_path_a()
965 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; in handle_path_a()
967 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f) in handle_path_a()
968 bw20powerlevel[RF90_PATH_A] = in handle_path_a()
969 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - in handle_path_a()
970 (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1); in handle_path_a()
972 bw20powerlevel[RF90_PATH_A] = in handle_path_a()
973 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + in handle_path_a()
974 rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]; in handle_path_a()
975 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf) in handle_path_a()
976 ofdmpowerlevel[RF90_PATH_A] = in handle_path_a()
977 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] - in handle_path_a()
978 (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1); in handle_path_a()
980 ofdmpowerlevel[RF90_PATH_A] = in handle_path_a()
981 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] + in handle_path_a()
982 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index]; in handle_path_a()
983 bw40powerlevel[RF90_PATH_A] = in handle_path_a()
984 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; in handle_path_a()
996 if (rf_path == RF90_PATH_A) { in _rtl88e_get_txpower_index()
1447 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1448 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1449 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1450 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl88e_phy_path_a_rx_iqk()
1489 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1490 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1491 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1492 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl88e_phy_path_a_rx_iqk()
1877 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1883 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1890 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1892 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl88e_phy_lc_calibrate()
1898 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl88e_phy_lc_calibrate()
2195 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl88ee_phy_set_rf_sleep()