Lines Matching refs:rt2x00dev
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_write() argument
70 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
76 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
86 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
89 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_read() argument
94 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
104 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
110 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
112 WAIT_FOR_BBP(rt2x00dev, ®); in rt61pci_bbp_read()
117 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
120 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt61pci_rf_write() argument
125 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
131 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt61pci_rf_write()
138 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
139 rt2x00_rf_write(rt2x00dev, word, value); in rt61pci_rf_write()
142 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
145 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, in rt61pci_mcu_request() argument
151 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
157 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt61pci_mcu_request()
162 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); in rt61pci_mcu_request()
167 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
170 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
176 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_read() local
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_eepromregister_read()
191 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_write() local
201 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
239 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt61pci_rfkill_poll() argument
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_rfkill_poll()
255 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); in rt61pci_brightness_set()
257 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); in rt61pci_brightness_set()
260 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
263 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
264 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
265 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
267 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
269 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
272 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
273 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
274 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
281 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, in rt61pci_brightness_set()
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); in rt61pci_blink_set()
297 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
302 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, in rt61pci_init_led() argument
306 led->rt2x00dev = rt2x00dev; in rt61pci_init_led()
317 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_shared_key() argument
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
358 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_shared_key()
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); in rt61pci_config_shared_key()
374 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); in rt61pci_config_shared_key()
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); in rt61pci_config_shared_key()
381 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); in rt61pci_config_shared_key()
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
409 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); in rt61pci_config_shared_key()
414 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_pairwise_key() argument
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
458 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
462 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); in rt61pci_config_pairwise_key()
472 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
509 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
515 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt61pci_config_filter() argument
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_filter()
537 !rt2x00dev->intf_ap_count); in rt61pci_config_filter()
544 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
547 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt61pci_config_intf() argument
558 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_intf()
560 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
568 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2, in rt61pci_config_intf()
577 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4, in rt61pci_config_intf()
583 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt61pci_config_erp() argument
589 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_erp()
592 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
595 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_erp()
599 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
603 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, in rt61pci_config_erp()
607 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_erp()
610 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
614 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_config_erp()
616 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
618 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); in rt61pci_config_erp()
622 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
626 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_5x() argument
633 rt61pci_bbp_read(rt2x00dev, 3, &r3); in rt61pci_config_antenna_5x()
634 rt61pci_bbp_read(rt2x00dev, 4, &r4); in rt61pci_config_antenna_5x()
635 rt61pci_bbp_read(rt2x00dev, 77, &r77); in rt61pci_config_antenna_5x()
637 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); in rt61pci_config_antenna_5x()
646 (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ)); in rt61pci_config_antenna_5x()
651 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
660 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
667 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_5x()
668 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_5x()
669 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_5x()
672 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2x() argument
679 rt61pci_bbp_read(rt2x00dev, 3, &r3); in rt61pci_config_antenna_2x()
680 rt61pci_bbp_read(rt2x00dev, 4, &r4); in rt61pci_config_antenna_2x()
681 rt61pci_bbp_read(rt2x00dev, 77, &r77); in rt61pci_config_antenna_2x()
683 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); in rt61pci_config_antenna_2x()
685 !rt2x00_has_cap_frame_type(rt2x00dev)); in rt61pci_config_antenna_2x()
705 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2x()
706 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2x()
707 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2x()
710 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529_rx() argument
715 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_config_antenna_2529_rx()
723 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
726 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529() argument
733 rt61pci_bbp_read(rt2x00dev, 3, &r3); in rt61pci_config_antenna_2529()
734 rt61pci_bbp_read(rt2x00dev, 4, &r4); in rt61pci_config_antenna_2529()
735 rt61pci_bbp_read(rt2x00dev, 77, &r77); in rt61pci_config_antenna_2529()
744 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); in rt61pci_config_antenna_2529()
756 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); in rt61pci_config_antenna_2529()
760 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2529()
761 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2529()
762 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2529()
796 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ant() argument
811 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { in rt61pci_config_ant()
813 lna = rt2x00_has_cap_external_lna_a(rt2x00dev); in rt61pci_config_ant()
816 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); in rt61pci_config_ant()
820 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); in rt61pci_config_ant()
822 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); in rt61pci_config_ant()
825 rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); in rt61pci_config_ant()
827 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); in rt61pci_config_ant()
829 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
831 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) in rt61pci_config_ant()
832 rt61pci_config_antenna_5x(rt2x00dev, ant); in rt61pci_config_ant()
833 else if (rt2x00_rf(rt2x00dev, RF2527)) in rt61pci_config_ant()
834 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
835 else if (rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_config_ant()
836 if (rt2x00_has_cap_double_antenna(rt2x00dev)) in rt61pci_config_ant()
837 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
839 rt61pci_config_antenna_2529(rt2x00dev, ant); in rt61pci_config_ant()
843 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, in rt61pci_config_lna_gain() argument
850 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) in rt61pci_config_lna_gain()
853 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); in rt61pci_config_lna_gain()
856 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) in rt61pci_config_lna_gain()
859 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); in rt61pci_config_lna_gain()
863 rt2x00dev->lna_gain = lna_gain; in rt61pci_config_lna_gain()
866 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt61pci_config_channel() argument
874 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
876 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); in rt61pci_config_channel()
878 rt61pci_bbp_read(rt2x00dev, 3, &r3); in rt61pci_config_channel()
880 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_channel()
887 rt61pci_bbp_write(rt2x00dev, 94, r94); in rt61pci_config_channel()
889 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
890 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
891 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
892 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
896 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
897 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
898 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); in rt61pci_config_channel()
899 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
903 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
904 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
905 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
906 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
911 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, in rt61pci_config_txpower() argument
916 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); in rt61pci_config_txpower()
917 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); in rt61pci_config_txpower()
918 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); in rt61pci_config_txpower()
919 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); in rt61pci_config_txpower()
921 rt61pci_config_channel(rt2x00dev, &rf, txpower); in rt61pci_config_txpower()
924 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt61pci_config_retry_limit() argument
929 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_retry_limit()
937 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
940 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ps() argument
949 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
951 rt2x00dev->beacon_int - 10); in rt61pci_config_ps()
958 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
963 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
965 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); in rt61pci_config_ps()
966 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); in rt61pci_config_ps()
968 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); in rt61pci_config_ps()
970 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
975 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
977 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
979 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); in rt61pci_config_ps()
980 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); in rt61pci_config_ps()
982 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); in rt61pci_config_ps()
986 static void rt61pci_config(struct rt2x00_dev *rt2x00dev, in rt61pci_config() argument
991 rt61pci_config_lna_gain(rt2x00dev, libconf); in rt61pci_config()
994 rt61pci_config_channel(rt2x00dev, &libconf->rf, in rt61pci_config()
998 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); in rt61pci_config()
1000 rt61pci_config_retry_limit(rt2x00dev, libconf); in rt61pci_config()
1002 rt61pci_config_ps(rt2x00dev, libconf); in rt61pci_config()
1008 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt61pci_link_stats() argument
1016 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_link_stats()
1022 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_link_stats()
1026 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt61pci_set_vgc() argument
1030 rt61pci_bbp_write(rt2x00dev, 17, vgc_level); in rt61pci_set_vgc()
1036 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_reset_tuner() argument
1039 rt61pci_set_vgc(rt2x00dev, qual, 0x20); in rt61pci_reset_tuner()
1042 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_link_tuner() argument
1051 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { in rt61pci_link_tuner()
1054 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { in rt61pci_link_tuner()
1061 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { in rt61pci_link_tuner()
1071 if (!rt2x00dev->intf_associated) in rt61pci_link_tuner()
1078 rt61pci_set_vgc(rt2x00dev, qual, 0x60); in rt61pci_link_tuner()
1086 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1094 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); in rt61pci_link_tuner()
1102 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); in rt61pci_link_tuner()
1115 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1126 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt61pci_link_tuner()
1128 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt61pci_link_tuner()
1136 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_start_queue() local
1141 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_start_queue()
1143 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1146 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_start_queue()
1150 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1159 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_kick_queue() local
1164 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1166 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1169 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1171 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1174 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1176 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1179 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1181 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1190 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_stop_queue() local
1195 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1197 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1200 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1202 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1205 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1207 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1210 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1212 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1215 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_stop_queue()
1217 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1220 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_stop_queue()
1224 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1229 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_stop_queue()
1239 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) in rt61pci_get_firmware_name() argument
1244 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); in rt61pci_get_firmware_name()
1263 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_check_firmware() argument
1292 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_load_firmware() argument
1302 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_load_firmware()
1309 rt2x00_err(rt2x00dev, "Unstable hardware\n"); in rt61pci_load_firmware()
1318 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1319 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_load_firmware()
1320 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); in rt61pci_load_firmware()
1321 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); in rt61pci_load_firmware()
1329 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1331 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, in rt61pci_load_firmware()
1335 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1341 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); in rt61pci_load_firmware()
1348 rt2x00_err(rt2x00dev, "MCU Control register not ready\n"); in rt61pci_load_firmware()
1363 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1365 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1368 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1370 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1372 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1420 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt61pci_init_queues() argument
1428 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); in rt61pci_init_queues()
1430 rt2x00dev->tx[0].limit); in rt61pci_init_queues()
1432 rt2x00dev->tx[1].limit); in rt61pci_init_queues()
1434 rt2x00dev->tx[2].limit); in rt61pci_init_queues()
1436 rt2x00dev->tx[3].limit); in rt61pci_init_queues()
1437 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1439 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); in rt61pci_init_queues()
1441 rt2x00dev->tx[0].desc_size / 4); in rt61pci_init_queues()
1442 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1444 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt61pci_init_queues()
1445 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); in rt61pci_init_queues()
1448 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1450 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt61pci_init_queues()
1451 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); in rt61pci_init_queues()
1454 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1456 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; in rt61pci_init_queues()
1457 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); in rt61pci_init_queues()
1460 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1462 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; in rt61pci_init_queues()
1463 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); in rt61pci_init_queues()
1466 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1468 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); in rt61pci_init_queues()
1469 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1471 rt2x00dev->rx->desc_size / 4); in rt61pci_init_queues()
1473 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1475 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt61pci_init_queues()
1476 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); in rt61pci_init_queues()
1479 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1481 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); in rt61pci_init_queues()
1486 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1488 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); in rt61pci_init_queues()
1493 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1495 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_init_queues()
1497 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1502 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt61pci_init_registers() argument
1506 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_init_registers()
1510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1512 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); in rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); in rt61pci_init_registers()
1535 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1540 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); in rt61pci_init_registers()
1547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1549 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); in rt61pci_init_registers()
1554 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); in rt61pci_init_registers()
1561 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1563 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_init_registers()
1570 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1572 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); in rt61pci_init_registers()
1574 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); in rt61pci_init_registers()
1576 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_init_registers()
1578 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1580 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); in rt61pci_init_registers()
1582 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt61pci_init_registers()
1585 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); in rt61pci_init_registers()
1591 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); in rt61pci_init_registers()
1592 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); in rt61pci_init_registers()
1593 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); in rt61pci_init_registers()
1595 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); in rt61pci_init_registers()
1596 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
1597 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); in rt61pci_init_registers()
1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); in rt61pci_init_registers()
1600 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); in rt61pci_init_registers()
1602 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); in rt61pci_init_registers()
1604 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_init_registers()
1612 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); in rt61pci_init_registers()
1613 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); in rt61pci_init_registers()
1614 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); in rt61pci_init_registers()
1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); in rt61pci_init_registers()
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_init_registers()
1623 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_init_registers()
1624 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); in rt61pci_init_registers()
1629 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1632 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1634 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1637 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1639 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1641 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1646 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt61pci_wait_bbp_ready() argument
1652 rt61pci_bbp_read(rt2x00dev, 0, &value); in rt61pci_wait_bbp_ready()
1658 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt61pci_wait_bbp_ready()
1662 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt61pci_init_bbp() argument
1669 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) in rt61pci_init_bbp()
1672 rt61pci_bbp_write(rt2x00dev, 3, 0x00); in rt61pci_init_bbp()
1673 rt61pci_bbp_write(rt2x00dev, 15, 0x30); in rt61pci_init_bbp()
1674 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); in rt61pci_init_bbp()
1675 rt61pci_bbp_write(rt2x00dev, 22, 0x38); in rt61pci_init_bbp()
1676 rt61pci_bbp_write(rt2x00dev, 23, 0x06); in rt61pci_init_bbp()
1677 rt61pci_bbp_write(rt2x00dev, 24, 0xfe); in rt61pci_init_bbp()
1678 rt61pci_bbp_write(rt2x00dev, 25, 0x0a); in rt61pci_init_bbp()
1679 rt61pci_bbp_write(rt2x00dev, 26, 0x0d); in rt61pci_init_bbp()
1680 rt61pci_bbp_write(rt2x00dev, 34, 0x12); in rt61pci_init_bbp()
1681 rt61pci_bbp_write(rt2x00dev, 37, 0x07); in rt61pci_init_bbp()
1682 rt61pci_bbp_write(rt2x00dev, 39, 0xf8); in rt61pci_init_bbp()
1683 rt61pci_bbp_write(rt2x00dev, 41, 0x60); in rt61pci_init_bbp()
1684 rt61pci_bbp_write(rt2x00dev, 53, 0x10); in rt61pci_init_bbp()
1685 rt61pci_bbp_write(rt2x00dev, 54, 0x18); in rt61pci_init_bbp()
1686 rt61pci_bbp_write(rt2x00dev, 60, 0x10); in rt61pci_init_bbp()
1687 rt61pci_bbp_write(rt2x00dev, 61, 0x04); in rt61pci_init_bbp()
1688 rt61pci_bbp_write(rt2x00dev, 62, 0x04); in rt61pci_init_bbp()
1689 rt61pci_bbp_write(rt2x00dev, 75, 0xfe); in rt61pci_init_bbp()
1690 rt61pci_bbp_write(rt2x00dev, 86, 0xfe); in rt61pci_init_bbp()
1691 rt61pci_bbp_write(rt2x00dev, 88, 0xfe); in rt61pci_init_bbp()
1692 rt61pci_bbp_write(rt2x00dev, 90, 0x0f); in rt61pci_init_bbp()
1693 rt61pci_bbp_write(rt2x00dev, 99, 0x00); in rt61pci_init_bbp()
1694 rt61pci_bbp_write(rt2x00dev, 102, 0x16); in rt61pci_init_bbp()
1695 rt61pci_bbp_write(rt2x00dev, 107, 0x04); in rt61pci_init_bbp()
1698 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); in rt61pci_init_bbp()
1703 rt61pci_bbp_write(rt2x00dev, reg_id, value); in rt61pci_init_bbp()
1713 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt61pci_toggle_irq() argument
1725 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1726 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1728 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1729 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1736 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1738 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1744 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1746 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1756 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1758 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1764 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt61pci_toggle_irq()
1765 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt61pci_toggle_irq()
1766 tasklet_kill(&rt2x00dev->autowake_tasklet); in rt61pci_toggle_irq()
1767 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_toggle_irq()
1771 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_enable_radio() argument
1778 if (unlikely(rt61pci_init_queues(rt2x00dev) || in rt61pci_enable_radio()
1779 rt61pci_init_registers(rt2x00dev) || in rt61pci_enable_radio()
1780 rt61pci_init_bbp(rt2x00dev))) in rt61pci_enable_radio()
1786 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_enable_radio()
1788 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1793 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_disable_radio() argument
1798 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); in rt61pci_disable_radio()
1801 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) in rt61pci_set_state() argument
1809 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); in rt61pci_set_state()
1812 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1820 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®2); in rt61pci_set_state()
1824 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1831 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt61pci_set_device_state() argument
1838 retval = rt61pci_enable_radio(rt2x00dev); in rt61pci_set_device_state()
1841 rt61pci_disable_radio(rt2x00dev); in rt61pci_set_device_state()
1845 rt61pci_toggle_irq(rt2x00dev, state); in rt61pci_set_device_state()
1851 retval = rt61pci_set_state(rt2x00dev, state); in rt61pci_set_device_state()
1859 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt61pci_set_device_state()
1909 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); in rt61pci_write_tx_desc()
1969 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_write_beacon() local
1979 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_write_beacon()
1982 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1992 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb); in rt61pci_write_beacon()
1999 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); in rt61pci_write_beacon()
2002 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_write_beacon()
2007 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base, in rt61pci_write_beacon()
2009 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, in rt61pci_write_beacon()
2019 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); in rt61pci_write_beacon()
2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2033 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_clear_beacon() local
2040 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); in rt61pci_clear_beacon()
2043 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
2048 rt2x00mmio_register_write(rt2x00dev, in rt61pci_clear_beacon()
2054 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_clear_beacon()
2060 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) in rt61pci_agc_to_rssi() argument
2062 u8 offset = rt2x00dev->lna_gain; in rt61pci_agc_to_rssi()
2080 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { in rt61pci_agc_to_rssi()
2091 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_fill_rxdone() local
2139 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); in rt61pci_fill_rxdone()
2153 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) in rt61pci_txdone() argument
2175 for (i = 0; i < rt2x00dev->tx->limit; i++) { in rt61pci_txdone()
2176 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); in rt61pci_txdone()
2185 queue = rt2x00queue_get_tx_queue(rt2x00dev, type); in rt61pci_txdone()
2210 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n", in rt61pci_txdone()
2244 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) in rt61pci_wakeup() argument
2246 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; in rt61pci_wakeup()
2248 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); in rt61pci_wakeup()
2251 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_interrupt() argument
2260 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2262 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_enable_interrupt()
2264 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2266 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2269 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_mcu_interrupt() argument
2278 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2280 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_enable_mcu_interrupt()
2282 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2284 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2289 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_txstatus_tasklet() local
2290 rt61pci_txdone(rt2x00dev); in rt61pci_txstatus_tasklet()
2291 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_txstatus_tasklet()
2292 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE); in rt61pci_txstatus_tasklet()
2297 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_tbtt_tasklet() local
2298 rt2x00lib_beacondone(rt2x00dev); in rt61pci_tbtt_tasklet()
2299 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_tbtt_tasklet()
2300 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE); in rt61pci_tbtt_tasklet()
2305 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_rxdone_tasklet() local
2306 if (rt2x00mmio_rxdone(rt2x00dev)) in rt61pci_rxdone_tasklet()
2307 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_rxdone_tasklet()
2308 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_rxdone_tasklet()
2309 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); in rt61pci_rxdone_tasklet()
2314 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_autowake_tasklet() local
2315 rt61pci_wakeup(rt2x00dev); in rt61pci_autowake_tasklet()
2316 rt2x00mmio_register_write(rt2x00dev, in rt61pci_autowake_tasklet()
2318 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_autowake_tasklet()
2319 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); in rt61pci_autowake_tasklet()
2324 struct rt2x00_dev *rt2x00dev = dev_instance; in rt61pci_interrupt() local
2332 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); in rt61pci_interrupt()
2333 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); in rt61pci_interrupt()
2335 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_interrupt()
2336 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2341 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_interrupt()
2348 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_interrupt()
2351 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt61pci_interrupt()
2354 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt61pci_interrupt()
2357 tasklet_schedule(&rt2x00dev->autowake_tasklet); in rt61pci_interrupt()
2371 spin_lock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2373 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_interrupt()
2375 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2377 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_interrupt()
2379 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2381 spin_unlock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2389 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_validate_eeprom() argument
2397 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_validate_eeprom()
2399 eeprom.data = rt2x00dev; in rt61pci_validate_eeprom()
2409 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt61pci_validate_eeprom()
2415 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt61pci_validate_eeprom()
2418 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac); in rt61pci_validate_eeprom()
2421 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); in rt61pci_validate_eeprom()
2432 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); in rt61pci_validate_eeprom()
2433 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); in rt61pci_validate_eeprom()
2436 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); in rt61pci_validate_eeprom()
2445 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); in rt61pci_validate_eeprom()
2446 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); in rt61pci_validate_eeprom()
2449 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); in rt61pci_validate_eeprom()
2453 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); in rt61pci_validate_eeprom()
2454 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); in rt61pci_validate_eeprom()
2457 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); in rt61pci_validate_eeprom()
2461 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); in rt61pci_validate_eeprom()
2462 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); in rt61pci_validate_eeprom()
2465 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); in rt61pci_validate_eeprom()
2469 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2470 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); in rt61pci_validate_eeprom()
2478 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2481 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); in rt61pci_validate_eeprom()
2485 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2486 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); in rt61pci_validate_eeprom()
2494 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2500 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_init_eeprom() argument
2509 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); in rt61pci_init_eeprom()
2515 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_init_eeprom()
2516 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), in rt61pci_init_eeprom()
2519 if (!rt2x00_rf(rt2x00dev, RF5225) && in rt61pci_init_eeprom()
2520 !rt2x00_rf(rt2x00dev, RF5325) && in rt61pci_init_eeprom()
2521 !rt2x00_rf(rt2x00dev, RF2527) && in rt61pci_init_eeprom()
2522 !rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_init_eeprom()
2523 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt61pci_init_eeprom()
2531 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2536 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2538 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2545 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2551 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2556 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); in rt61pci_init_eeprom()
2558 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2560 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); in rt61pci_init_eeprom()
2565 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); in rt61pci_init_eeprom()
2568 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2570 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2577 if (rt2x00_rf(rt2x00dev, RF2529) && in rt61pci_init_eeprom()
2578 !rt2x00_has_cap_double_antenna(rt2x00dev)) { in rt61pci_init_eeprom()
2579 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2581 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2585 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2587 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2596 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); in rt61pci_init_eeprom()
2599 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt61pci_init_eeprom()
2600 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); in rt61pci_init_eeprom()
2602 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt61pci_init_eeprom()
2605 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); in rt61pci_init_eeprom()
2606 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, in rt61pci_init_eeprom()
2609 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, in rt61pci_init_eeprom()
2612 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, in rt61pci_init_eeprom()
2615 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, in rt61pci_init_eeprom()
2618 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, in rt61pci_init_eeprom()
2621 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, in rt61pci_init_eeprom()
2623 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, in rt61pci_init_eeprom()
2626 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, in rt61pci_init_eeprom()
2748 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw_mode() argument
2750 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt61pci_probe_hw_mode()
2758 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; in rt61pci_probe_hw_mode()
2763 rt2x00dev->hw->flags = in rt61pci_probe_hw_mode()
2769 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt61pci_probe_hw_mode()
2770 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt61pci_probe_hw_mode()
2771 rt2x00_eeprom_addr(rt2x00dev, in rt61pci_probe_hw_mode()
2783 rt2x00dev->hw->max_rates = 1; in rt61pci_probe_hw_mode()
2784 rt2x00dev->hw->max_report_rates = 7; in rt61pci_probe_hw_mode()
2785 rt2x00dev->hw->max_rate_tries = 1; in rt61pci_probe_hw_mode()
2793 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) { in rt61pci_probe_hw_mode()
2801 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { in rt61pci_probe_hw_mode()
2815 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); in rt61pci_probe_hw_mode()
2822 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); in rt61pci_probe_hw_mode()
2833 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw() argument
2841 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); in rt61pci_probe_hw()
2846 retval = rt61pci_validate_eeprom(rt2x00dev); in rt61pci_probe_hw()
2850 retval = rt61pci_init_eeprom(rt2x00dev); in rt61pci_probe_hw()
2858 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_probe_hw()
2860 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2865 retval = rt61pci_probe_hw_mode(rt2x00dev); in rt61pci_probe_hw()
2873 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2878 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2879 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2881 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2882 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2887 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt61pci_probe_hw()
2899 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_conf_tx() local
2923 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt61pci_conf_tx()
2930 rt2x00mmio_register_read(rt2x00dev, offset, ®); in rt61pci_conf_tx()
2932 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2938 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); in rt61pci_conf_tx()
2940 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2942 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); in rt61pci_conf_tx()
2944 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2946 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); in rt61pci_conf_tx()
2948 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()
2955 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_get_tsf() local
2959 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); in rt61pci_get_tsf()
2961 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); in rt61pci_get_tsf()