Lines Matching refs:FIELD32
136 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
137 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
138 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
139 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
140 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
141 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
142 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
148 #define AUX_OPT_BIT0 FIELD32(0x00000001)
149 #define AUX_OPT_BIT1 FIELD32(0x00000002)
150 #define AUX_OPT_BIT2 FIELD32(0x00000004)
151 #define AUX_OPT_BIT3 FIELD32(0x00000008)
152 #define AUX_OPT_BIT4 FIELD32(0x00000010)
153 #define AUX_OPT_BIT5 FIELD32(0x00000020)
154 #define AUX_OPT_BIT6 FIELD32(0x00000040)
155 #define AUX_OPT_BIT7 FIELD32(0x00000080)
156 #define AUX_OPT_BIT8 FIELD32(0x00000100)
157 #define AUX_OPT_BIT9 FIELD32(0x00000200)
158 #define AUX_OPT_BIT10 FIELD32(0x00000400)
159 #define AUX_OPT_BIT11 FIELD32(0x00000800)
160 #define AUX_OPT_BIT12 FIELD32(0x00001000)
161 #define AUX_OPT_BIT13 FIELD32(0x00002000)
162 #define AUX_OPT_BIT14 FIELD32(0x00004000)
163 #define AUX_OPT_BIT15 FIELD32(0x00008000)
164 #define LDO25_LEVEL FIELD32(0x00030000)
165 #define LDO25_LARGEA FIELD32(0x00040000)
166 #define LDO25_FRC_ON FIELD32(0x00080000)
167 #define CMB_RSV FIELD32(0x00300000)
168 #define XTAL_RDY FIELD32(0x00400000)
169 #define PLL_LD FIELD32(0x00800000)
170 #define LDO_CORE_LEVEL FIELD32(0x0F000000)
171 #define LDO_BGSEL FIELD32(0x30000000)
172 #define LDO3_EN FIELD32(0x40000000)
173 #define LDO0_EN FIELD32(0x80000000)
205 #define OSC_REF_CYCLE FIELD32(0x00001fff)
206 #define OSC_RSV FIELD32(0x0000e000)
207 #define OSC_CAL_CNT FIELD32(0x0fff0000)
208 #define OSC_CAL_ACK FIELD32(0x10000000)
209 #define OSC_CLK_32K_VLD FIELD32(0x20000000)
210 #define OSC_CAL_REQ FIELD32(0x40000000)
211 #define OSC_ROSC_EN FIELD32(0x80000000)
217 #define COEX_CFG_ANT FIELD32(0xff000000)
227 #define BT_COEX_CFG1 FIELD32(0xff000000)
228 #define BT_COEX_CFG0 FIELD32(0x00ff0000)
229 #define WL_COEX_CFG1 FIELD32(0x0000ff00)
230 #define WL_COEX_CFG0 FIELD32(0x000000ff)
236 #define PLL_RESERVED_INPUT1 FIELD32(0x000000ff)
237 #define PLL_RESERVED_INPUT2 FIELD32(0x0000ff00)
238 #define PLL_CONTROL FIELD32(0x00070000)
239 #define PLL_LPF_R1 FIELD32(0x00080000)
240 #define PLL_LPF_C1_CTRL FIELD32(0x00300000)
241 #define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
242 #define PLL_CP_CURRENT_CTRL FIELD32(0x03000000)
243 #define PLL_PFD_DELAY_CTRL FIELD32(0x0c000000)
244 #define PLL_LOCK_CTRL FIELD32(0x70000000)
245 #define PLL_VBGBK_EN FIELD32(0x80000000)
253 #define WLAN_EN FIELD32(0x00000001)
254 #define WLAN_CLK_EN FIELD32(0x00000002)
255 #define WLAN_RSV1 FIELD32(0x00000004)
256 #define WLAN_RESET FIELD32(0x00000008)
257 #define PCIE_APP0_CLK_REQ FIELD32(0x00000010)
258 #define FRC_WL_ANT_SET FIELD32(0x00000020)
259 #define INV_TR_SW0 FIELD32(0x00000040)
260 #define WLAN_GPIO_IN_BIT0 FIELD32(0x00000100)
261 #define WLAN_GPIO_IN_BIT1 FIELD32(0x00000200)
262 #define WLAN_GPIO_IN_BIT2 FIELD32(0x00000400)
263 #define WLAN_GPIO_IN_BIT3 FIELD32(0x00000800)
264 #define WLAN_GPIO_IN_BIT4 FIELD32(0x00001000)
265 #define WLAN_GPIO_IN_BIT5 FIELD32(0x00002000)
266 #define WLAN_GPIO_IN_BIT6 FIELD32(0x00004000)
267 #define WLAN_GPIO_IN_BIT7 FIELD32(0x00008000)
268 #define WLAN_GPIO_IN_BIT_ALL FIELD32(0x0000ff00)
269 #define WLAN_GPIO_OUT_BIT0 FIELD32(0x00010000)
270 #define WLAN_GPIO_OUT_BIT1 FIELD32(0x00020000)
271 #define WLAN_GPIO_OUT_BIT2 FIELD32(0x00040000)
272 #define WLAN_GPIO_OUT_BIT3 FIELD32(0x00050000)
273 #define WLAN_GPIO_OUT_BIT4 FIELD32(0x00100000)
274 #define WLAN_GPIO_OUT_BIT5 FIELD32(0x00200000)
275 #define WLAN_GPIO_OUT_BIT6 FIELD32(0x00400000)
276 #define WLAN_GPIO_OUT_BIT7 FIELD32(0x00800000)
277 #define WLAN_GPIO_OUT_BIT_ALL FIELD32(0x00ff0000)
278 #define WLAN_GPIO_OUT_OE_BIT0 FIELD32(0x01000000)
279 #define WLAN_GPIO_OUT_OE_BIT1 FIELD32(0x02000000)
280 #define WLAN_GPIO_OUT_OE_BIT2 FIELD32(0x04000000)
281 #define WLAN_GPIO_OUT_OE_BIT3 FIELD32(0x08000000)
282 #define WLAN_GPIO_OUT_OE_BIT4 FIELD32(0x10000000)
283 #define WLAN_GPIO_OUT_OE_BIT5 FIELD32(0x20000000)
284 #define WLAN_GPIO_OUT_OE_BIT6 FIELD32(0x40000000)
285 #define WLAN_GPIO_OUT_OE_BIT7 FIELD32(0x80000000)
286 #define WLAN_GPIO_OUT_OE_BIT_ALL FIELD32(0xff000000)
292 #define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
293 #define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
299 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
307 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
308 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
309 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
310 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
311 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
312 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
313 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
314 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
315 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
316 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
317 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
318 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
319 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
320 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
321 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
322 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
323 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
324 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
330 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
331 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
332 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
333 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
334 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
335 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
336 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
337 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
338 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
339 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
340 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
341 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
342 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
343 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
344 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
345 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
346 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
347 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
353 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
354 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
355 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
356 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
357 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
358 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
359 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
360 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
361 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
367 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
368 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
369 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
370 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
371 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
372 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
373 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
379 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
380 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
381 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
382 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
383 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
384 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
394 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
395 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
396 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
397 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
407 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
408 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
409 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
410 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
420 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
421 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
422 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
423 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
431 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
432 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
440 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
441 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
449 #define GPIO_CTRL_VAL0 FIELD32(0x00000001)
450 #define GPIO_CTRL_VAL1 FIELD32(0x00000002)
451 #define GPIO_CTRL_VAL2 FIELD32(0x00000004)
452 #define GPIO_CTRL_VAL3 FIELD32(0x00000008)
453 #define GPIO_CTRL_VAL4 FIELD32(0x00000010)
454 #define GPIO_CTRL_VAL5 FIELD32(0x00000020)
455 #define GPIO_CTRL_VAL6 FIELD32(0x00000040)
456 #define GPIO_CTRL_VAL7 FIELD32(0x00000080)
457 #define GPIO_CTRL_DIR0 FIELD32(0x00000100)
458 #define GPIO_CTRL_DIR1 FIELD32(0x00000200)
459 #define GPIO_CTRL_DIR2 FIELD32(0x00000400)
460 #define GPIO_CTRL_DIR3 FIELD32(0x00000800)
461 #define GPIO_CTRL_DIR4 FIELD32(0x00001000)
462 #define GPIO_CTRL_DIR5 FIELD32(0x00002000)
463 #define GPIO_CTRL_DIR6 FIELD32(0x00004000)
464 #define GPIO_CTRL_DIR7 FIELD32(0x00008000)
465 #define GPIO_CTRL_VAL8 FIELD32(0x00010000)
466 #define GPIO_CTRL_VAL9 FIELD32(0x00020000)
467 #define GPIO_CTRL_VAL10 FIELD32(0x00040000)
468 #define GPIO_CTRL_DIR8 FIELD32(0x01000000)
469 #define GPIO_CTRL_DIR9 FIELD32(0x02000000)
470 #define GPIO_CTRL_DIR10 FIELD32(0x04000000)
548 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
549 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
550 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
551 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
552 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
553 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
554 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
555 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
556 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
557 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
558 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
567 #define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
568 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
575 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
576 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
582 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
598 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
599 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
600 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
601 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
607 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
608 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
609 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
610 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
620 #define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
621 #define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
622 #define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
623 #define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
635 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
636 #define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
637 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
638 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
644 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
645 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
646 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
647 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
673 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
674 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
675 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
676 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
677 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
678 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
679 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
685 #define GPIO_SWITCH_0 FIELD32(0x00000001)
686 #define GPIO_SWITCH_1 FIELD32(0x00000002)
687 #define GPIO_SWITCH_2 FIELD32(0x00000004)
688 #define GPIO_SWITCH_3 FIELD32(0x00000008)
689 #define GPIO_SWITCH_4 FIELD32(0x00000010)
690 #define GPIO_SWITCH_5 FIELD32(0x00000020)
691 #define GPIO_SWITCH_6 FIELD32(0x00000040)
692 #define GPIO_SWITCH_7 FIELD32(0x00000080)
698 #define MAC_DEBUG_INDEX_XTAL FIELD32(0x80000000)
711 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
712 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
718 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
719 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
720 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
721 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
722 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
723 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
724 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
725 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
731 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
732 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
733 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
734 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
745 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
746 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
747 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
753 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
754 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
755 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
756 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
770 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
771 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
772 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
773 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
782 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
783 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
784 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
785 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
797 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
798 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
799 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
800 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
801 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
802 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
813 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
814 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
815 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
816 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
817 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
818 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
828 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
829 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
836 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
853 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
854 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
855 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
856 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
857 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
858 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
859 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
870 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
871 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
884 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
885 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
886 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
887 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
888 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
894 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
895 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
901 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
902 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
903 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
904 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
915 #define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
916 #define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
917 #define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
918 #define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
919 #define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
934 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
935 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
936 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
937 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
938 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
939 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
947 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
948 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
949 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
950 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
956 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
962 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
975 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
976 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
982 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
983 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
1006 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
1019 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
1020 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
1021 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
1027 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
1028 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
1029 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
1030 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
1036 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
1037 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
1038 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
1039 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
1045 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
1046 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
1047 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
1048 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
1054 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
1055 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
1056 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
1057 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
1067 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
1068 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
1069 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
1070 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
1071 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
1072 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
1073 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
1074 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
1080 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
1081 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
1082 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
1083 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
1084 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
1085 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
1086 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
1087 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
1089 #define TX_PWR_CFG_0_CCK1_CH0 FIELD32(0x0000000f)
1090 #define TX_PWR_CFG_0_CCK1_CH1 FIELD32(0x000000f0)
1091 #define TX_PWR_CFG_0_CCK5_CH0 FIELD32(0x00000f00)
1092 #define TX_PWR_CFG_0_CCK5_CH1 FIELD32(0x0000f000)
1093 #define TX_PWR_CFG_0_OFDM6_CH0 FIELD32(0x000f0000)
1094 #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000)
1095 #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000)
1096 #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000)
1102 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
1103 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
1104 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
1105 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
1106 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
1107 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
1108 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
1109 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
1111 #define TX_PWR_CFG_1_OFDM24_CH0 FIELD32(0x0000000f)
1112 #define TX_PWR_CFG_1_OFDM24_CH1 FIELD32(0x000000f0)
1113 #define TX_PWR_CFG_1_OFDM48_CH0 FIELD32(0x00000f00)
1114 #define TX_PWR_CFG_1_OFDM48_CH1 FIELD32(0x0000f000)
1115 #define TX_PWR_CFG_1_MCS0_CH0 FIELD32(0x000f0000)
1116 #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000)
1117 #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000)
1118 #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000)
1124 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
1125 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
1126 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
1127 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
1128 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
1129 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
1130 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
1131 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
1133 #define TX_PWR_CFG_2_MCS4_CH0 FIELD32(0x0000000f)
1134 #define TX_PWR_CFG_2_MCS4_CH1 FIELD32(0x000000f0)
1135 #define TX_PWR_CFG_2_MCS6_CH0 FIELD32(0x00000f00)
1136 #define TX_PWR_CFG_2_MCS6_CH1 FIELD32(0x0000f000)
1137 #define TX_PWR_CFG_2_MCS8_CH0 FIELD32(0x000f0000)
1138 #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000)
1139 #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000)
1140 #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000)
1146 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
1147 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
1148 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
1149 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
1150 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
1151 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
1152 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
1153 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
1155 #define TX_PWR_CFG_3_MCS12_CH0 FIELD32(0x0000000f)
1156 #define TX_PWR_CFG_3_MCS12_CH1 FIELD32(0x000000f0)
1157 #define TX_PWR_CFG_3_MCS14_CH0 FIELD32(0x00000f00)
1158 #define TX_PWR_CFG_3_MCS14_CH1 FIELD32(0x0000f000)
1159 #define TX_PWR_CFG_3_STBC0_CH0 FIELD32(0x000f0000)
1160 #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000)
1161 #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000)
1162 #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000)
1168 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
1169 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
1170 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
1171 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
1173 #define TX_PWR_CFG_3_STBC4_CH0 FIELD32(0x0000000f)
1174 #define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0)
1175 #define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00)
1176 #define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000)
1183 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
1184 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
1185 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
1186 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
1187 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
1188 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
1189 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
1190 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
1191 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
1192 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
1193 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
1194 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
1195 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
1196 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
1197 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
1198 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
1199 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
1200 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
1201 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
1202 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
1203 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
1204 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
1205 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
1206 #define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
1207 #define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
1208 #define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
1209 #define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1210 #define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1216 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1217 #define TX_BAND_CFG_A FIELD32(0x00000002)
1218 #define TX_BAND_CFG_BG FIELD32(0x00000004)
1257 #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1258 #define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1259 #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1260 #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1261 #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1262 #define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1263 #define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1264 #define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1265 #define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1266 #define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1274 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1275 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1276 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1287 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1288 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1289 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1303 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1304 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1305 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1306 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1307 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1308 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1323 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1324 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1325 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1326 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1327 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1328 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1329 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1330 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1336 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1337 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1338 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1339 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1340 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1341 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1342 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1343 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1349 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1350 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1351 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1352 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1353 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1354 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1355 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1356 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1362 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1363 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1364 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1365 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1366 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1367 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1368 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1369 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1375 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1376 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1377 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1378 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1396 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1397 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1398 #define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1399 #define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1400 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1401 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1402 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1403 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1404 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1405 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1406 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1412 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1413 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1414 #define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1415 #define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1416 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1417 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1418 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1419 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1420 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1421 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1422 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1428 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1429 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1430 #define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1431 #define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1432 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1433 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1434 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1435 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1436 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1437 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1438 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1444 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1445 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1446 #define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1447 #define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1448 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1449 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1450 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1451 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1452 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1453 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1454 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1460 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1461 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1462 #define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1463 #define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1464 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1465 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1466 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1467 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1468 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1469 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1470 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1476 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1477 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1478 #define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1479 #define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1480 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1481 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1482 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1483 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1484 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1485 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1486 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1500 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
1501 #define TX_PWR_CFG_5_MCS16_CH1 FIELD32(0x000000f0)
1502 #define TX_PWR_CFG_5_MCS16_CH2 FIELD32(0x00000f00)
1503 #define TX_PWR_CFG_5_MCS18_CH0 FIELD32(0x000f0000)
1504 #define TX_PWR_CFG_5_MCS18_CH1 FIELD32(0x00f00000)
1505 #define TX_PWR_CFG_5_MCS18_CH2 FIELD32(0x0f000000)
1509 #define TX_PWR_CFG_6_MCS20_CH0 FIELD32(0x0000000f)
1510 #define TX_PWR_CFG_6_MCS20_CH1 FIELD32(0x000000f0)
1511 #define TX_PWR_CFG_6_MCS20_CH2 FIELD32(0x00000f00)
1512 #define TX_PWR_CFG_6_MCS22_CH0 FIELD32(0x000f0000)
1513 #define TX_PWR_CFG_6_MCS22_CH1 FIELD32(0x00f00000)
1514 #define TX_PWR_CFG_6_MCS22_CH2 FIELD32(0x0f000000)
1518 #define TX_PWR_CFG_0_EXT_CCK1_CH2 FIELD32(0x0000000f)
1519 #define TX_PWR_CFG_0_EXT_CCK5_CH2 FIELD32(0x00000f00)
1520 #define TX_PWR_CFG_0_EXT_OFDM6_CH2 FIELD32(0x000f0000)
1521 #define TX_PWR_CFG_0_EXT_OFDM12_CH2 FIELD32(0x0f000000)
1525 #define TX_PWR_CFG_1_EXT_OFDM24_CH2 FIELD32(0x0000000f)
1526 #define TX_PWR_CFG_1_EXT_OFDM48_CH2 FIELD32(0x00000f00)
1527 #define TX_PWR_CFG_1_EXT_MCS0_CH2 FIELD32(0x000f0000)
1528 #define TX_PWR_CFG_1_EXT_MCS2_CH2 FIELD32(0x0f000000)
1532 #define TX_PWR_CFG_2_EXT_MCS4_CH2 FIELD32(0x0000000f)
1533 #define TX_PWR_CFG_2_EXT_MCS6_CH2 FIELD32(0x00000f00)
1534 #define TX_PWR_CFG_2_EXT_MCS8_CH2 FIELD32(0x000f0000)
1535 #define TX_PWR_CFG_2_EXT_MCS10_CH2 FIELD32(0x0f000000)
1539 #define TX_PWR_CFG_3_EXT_MCS12_CH2 FIELD32(0x0000000f)
1540 #define TX_PWR_CFG_3_EXT_MCS14_CH2 FIELD32(0x00000f00)
1541 #define TX_PWR_CFG_3_EXT_STBC0_CH2 FIELD32(0x000f0000)
1542 #define TX_PWR_CFG_3_EXT_STBC2_CH2 FIELD32(0x0f000000)
1546 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
1547 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
1551 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
1552 #define TX_PWR_CFG_7_OFDM54_CH1 FIELD32(0x000000f0)
1553 #define TX_PWR_CFG_7_OFDM54_CH2 FIELD32(0x00000f00)
1554 #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000)
1555 #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000)
1556 #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000)
1560 #define TX_PWR_CFG_8_MCS15_CH0 FIELD32(0x0000000f)
1561 #define TX_PWR_CFG_8_MCS15_CH1 FIELD32(0x000000f0)
1562 #define TX_PWR_CFG_8_MCS15_CH2 FIELD32(0x00000f00)
1563 #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000)
1564 #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000)
1565 #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000)
1569 #define TX_PWR_CFG_9_STBC7_CH0 FIELD32(0x0000000f)
1570 #define TX_PWR_CFG_9_STBC7_CH1 FIELD32(0x000000f0)
1571 #define TX_PWR_CFG_9_STBC7_CH2 FIELD32(0x00000f00)
1577 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1578 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1579 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1580 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1581 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1582 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1583 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1584 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1585 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1586 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1587 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1588 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1589 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1590 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1591 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1592 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1593 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1606 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1607 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1608 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1609 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1610 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1611 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1612 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1689 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1690 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1696 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1697 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1703 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1704 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1710 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1711 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1717 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1718 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1724 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1725 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1752 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1753 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1754 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1755 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1756 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1757 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1758 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1759 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1760 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1761 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1762 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1768 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1769 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1775 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1776 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1782 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1783 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1789 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1790 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1796 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1797 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1803 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1804 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1810 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1811 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1817 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1818 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1824 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1825 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1833 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1834 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1901 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1902 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1903 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1904 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1905 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1906 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1907 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1908 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1913 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1914 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1915 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1916 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1917 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1918 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1919 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1920 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1931 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1932 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1933 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1934 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1942 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1943 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1944 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1945 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
2357 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
2358 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
2359 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
2364 #define RF3_TXPOWER_G FIELD32(0x00003e00)
2365 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
2366 #define RF3_TXPOWER_A FIELD32(0x00003c00)
2371 #define RF4_TXPOWER_G FIELD32(0x000007c0)
2372 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
2373 #define RF4_TXPOWER_A FIELD32(0x00000780)
2374 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
2375 #define RF4_HT40 FIELD32(0x00200000)
2846 #define TXWI_W0_FRAG FIELD32(0x00000001)
2847 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2848 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2849 #define TXWI_W0_TS FIELD32(0x00000008)
2850 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2851 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2852 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2853 #define TXWI_W0_MCS FIELD32(0x007f0000)
2854 #define TXWI_W0_BW FIELD32(0x00800000)
2855 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2856 #define TXWI_W0_STBC FIELD32(0x06000000)
2857 #define TXWI_W0_IFS FIELD32(0x08000000)
2858 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2876 #define TXWI_W1_ACK FIELD32(0x00000001)
2877 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2878 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2879 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2880 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2881 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2882 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2883 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2888 #define TXWI_W2_IV FIELD32(0xffffffff)
2893 #define TXWI_W3_EIV FIELD32(0xffffffff)
2902 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2903 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2904 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2905 #define RXWI_W0_UDF FIELD32(0x0000e000)
2906 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2907 #define RXWI_W0_TID FIELD32(0xf0000000)
2912 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2913 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2914 #define RXWI_W1_MCS FIELD32(0x007f0000)
2915 #define RXWI_W1_BW FIELD32(0x00800000)
2916 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2917 #define RXWI_W1_STBC FIELD32(0x06000000)
2918 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2923 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2924 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2925 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2930 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2931 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)