Lines Matching refs:FIELD32
66 #define CSR0_REVISION FIELD32(0x0000ffff)
75 #define CSR1_SOFT_RESET FIELD32(0x00000001)
76 #define CSR1_BBP_RESET FIELD32(0x00000002)
77 #define CSR1_HOST_READY FIELD32(0x00000004)
88 #define CSR3_BYTE0 FIELD32(0x000000ff)
89 #define CSR3_BYTE1 FIELD32(0x0000ff00)
90 #define CSR3_BYTE2 FIELD32(0x00ff0000)
91 #define CSR3_BYTE3 FIELD32(0xff000000)
97 #define CSR4_BYTE4 FIELD32(0x000000ff)
98 #define CSR4_BYTE5 FIELD32(0x0000ff00)
104 #define CSR5_BYTE0 FIELD32(0x000000ff)
105 #define CSR5_BYTE1 FIELD32(0x0000ff00)
106 #define CSR5_BYTE2 FIELD32(0x00ff0000)
107 #define CSR5_BYTE3 FIELD32(0xff000000)
113 #define CSR6_BYTE4 FIELD32(0x000000ff)
114 #define CSR6_BYTE5 FIELD32(0x0000ff00)
128 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
129 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
130 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
131 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
132 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
133 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
134 #define CSR7_RXDONE FIELD32(0x00000040)
148 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
149 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
150 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
151 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
152 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
153 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
154 #define CSR8_RXDONE FIELD32(0x00000040)
161 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
172 #define CSR11_CWMIN FIELD32(0x0000000f)
173 #define CSR11_CWMAX FIELD32(0x000000f0)
174 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
175 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
176 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
185 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
186 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
195 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
196 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
210 #define CSR14_TSF_COUNT FIELD32(0x00000001)
211 #define CSR14_TSF_SYNC FIELD32(0x00000006)
212 #define CSR14_TBCN FIELD32(0x00000008)
213 #define CSR14_TCFP FIELD32(0x00000010)
214 #define CSR14_TATIMW FIELD32(0x00000020)
215 #define CSR14_BEACON_GEN FIELD32(0x00000040)
216 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
217 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
226 #define CSR15_CFP FIELD32(0x00000001)
227 #define CSR15_ATIMW FIELD32(0x00000002)
228 #define CSR15_BEACON_SENT FIELD32(0x00000004)
234 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
240 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
248 #define CSR18_SIFS FIELD32(0x0000ffff)
249 #define CSR18_PIFS FIELD32(0xffff0000)
257 #define CSR19_DIFS FIELD32(0x0000ffff)
258 #define CSR19_EIFS FIELD32(0xffff0000)
267 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
268 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
269 #define CSR20_AUTOWAKE FIELD32(0x01000000)
277 #define CSR21_RELOAD FIELD32(0x00000001)
278 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
279 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
280 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
281 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
282 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
290 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
291 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
306 #define TXCSR0_KICK_TX FIELD32(0x00000001)
307 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
308 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
309 #define TXCSR0_ABORT FIELD32(0x00000008)
319 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
320 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
321 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
322 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
332 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
333 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
334 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
335 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
341 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
347 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
353 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
359 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
366 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
385 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
386 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
387 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
388 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
389 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
390 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
391 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
392 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
400 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
401 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
407 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
415 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
416 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
417 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
418 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
419 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
420 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
421 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
422 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
430 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
431 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
432 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
433 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
441 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
442 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
443 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
444 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
452 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
453 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
454 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
455 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
473 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
474 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
475 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
476 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
477 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
484 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
530 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
531 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
532 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
533 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
534 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
535 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
544 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
545 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
546 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
564 #define MACCSR1_KICK_RX FIELD32(0x00000001)
565 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
566 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
567 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
568 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
569 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
570 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
578 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
579 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
580 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
581 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
592 #define BCNCSR_CHANGE FIELD32(0x00000001)
593 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
594 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
595 #define BCNCSR_MODE FIELD32(0x00006000)
596 #define BCNCSR_PLUS FIELD32(0x00008000)
610 #define BBPCSR_VALUE FIELD32(0x000000ff)
611 #define BBPCSR_REGNUM FIELD32(0x00007f00)
612 #define BBPCSR_BUSY FIELD32(0x00008000)
613 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
624 #define RFCSR_VALUE FIELD32(0x00ffffff)
625 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
626 #define RFCSR_IF_SELECT FIELD32(0x20000000)
627 #define RFCSR_PLL_LD FIELD32(0x40000000)
628 #define RFCSR_BUSY FIELD32(0x80000000)
638 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
639 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
640 #define LEDCSR_LINK FIELD32(0x00010000)
641 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
665 #define GPIOCSR_VAL0 FIELD32(0x00000001)
666 #define GPIOCSR_VAL1 FIELD32(0x00000002)
667 #define GPIOCSR_VAL2 FIELD32(0x00000004)
668 #define GPIOCSR_VAL3 FIELD32(0x00000008)
669 #define GPIOCSR_VAL4 FIELD32(0x00000010)
670 #define GPIOCSR_VAL5 FIELD32(0x00000020)
671 #define GPIOCSR_VAL6 FIELD32(0x00000040)
672 #define GPIOCSR_VAL7 FIELD32(0x00000080)
673 #define GPIOCSR_DIR0 FIELD32(0x00000100)
674 #define GPIOCSR_DIR1 FIELD32(0x00000200)
675 #define GPIOCSR_DIR2 FIELD32(0x00000400)
676 #define GPIOCSR_DIR3 FIELD32(0x00000800)
677 #define GPIOCSR_DIR4 FIELD32(0x00001000)
678 #define GPIOCSR_DIR5 FIELD32(0x00002000)
679 #define GPIOCSR_DIR6 FIELD32(0x00004000)
680 #define GPIOCSR_DIR7 FIELD32(0x00008000)
692 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
699 #define MACCSR2_DELAY FIELD32(0x000000ff)
705 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
706 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
707 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
708 #define ARCSR2_LENGTH FIELD32(0xffff0000)
714 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
715 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
716 #define ARCSR3_LENGTH FIELD32(0xffff0000)
722 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
723 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
724 #define ARCSR4_LENGTH FIELD32(0xffff0000)
730 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
731 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
732 #define ARCSR5_LENGTH FIELD32(0xffff0000)
756 #define RF1_TUNER FIELD32(0x00020000)
761 #define RF3_TUNER FIELD32(0x00000100)
762 #define RF3_TXPOWER FIELD32(0x00003e00)
830 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
831 #define TXD_W0_VALID FIELD32(0x00000002)
832 #define TXD_W0_RESULT FIELD32(0x0000001c)
833 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
834 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
835 #define TXD_W0_ACK FIELD32(0x00000200)
836 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
837 #define TXD_W0_RTS FIELD32(0x00000800)
838 #define TXD_W0_IFS FIELD32(0x00006000)
839 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
840 #define TXD_W0_AGC FIELD32(0x00ff0000)
841 #define TXD_W0_R2 FIELD32(0xff000000)
846 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
851 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
852 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
858 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
859 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
860 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
861 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
862 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
863 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
865 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
866 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
867 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
868 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
869 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
870 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
875 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
876 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
877 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
878 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
879 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
884 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
889 #define TXD_W7_RESERVED FIELD32(0xffffffff)
898 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
899 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
900 #define RXD_W0_MULTICAST FIELD32(0x00000004)
901 #define RXD_W0_BROADCAST FIELD32(0x00000008)
902 #define RXD_W0_MY_BSS FIELD32(0x00000010)
903 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
904 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
905 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
910 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
915 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
916 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
917 #define RXD_W2_SIGNAL FIELD32(0xff000000)
922 #define RXD_W3_RSSI FIELD32(0x000000ff)
923 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
924 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
925 #define RXD_W3_BBR5 FIELD32(0xff000000)
930 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
935 #define RXD_W5_RESERVED FIELD32(0xffffffff)
936 #define RXD_W6_RESERVED FIELD32(0xffffffff)
937 #define RXD_W7_RESERVED FIELD32(0xffffffff)