Lines Matching refs:cpu_to_le32
377 #define UCODE_VALID_OK cpu_to_le32(0x1)
536 #define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
537 #define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
539 #define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
541 #define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
543 #define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
544 #define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
546 #define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
547 #define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
548 #define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
549 #define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
551 #define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
552 #define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
555 #define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
560 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
564 #define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
565 #define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
568 #define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
577 #define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
578 #define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
579 #define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
582 #define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
586 #define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
588 #define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
590 #define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
592 #define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
594 #define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
596 #define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
598 #define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
761 #define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
762 #define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
763 #define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
798 #define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
799 #define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
800 #define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
801 #define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
802 #define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
804 #define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
805 #define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
806 #define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
808 #define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
1051 #define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1052 #define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1161 #define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1166 #define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1174 #define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1178 #define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1181 #define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1185 #define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1191 #define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1195 #define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1200 #define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1208 #define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1212 #define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1215 #define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1915 #define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1916 #define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1917 #define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1918 #define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1989 #define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
2249 #define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2250 #define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2289 #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2306 #define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2414 #define CAN_ABORT_STATUS cpu_to_le32(0x1)
2579 #define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2760 #define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1) /* see above */
2761 #define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)/* see above */
2781 #define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2782 #define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
3170 #define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3177 #define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3187 #define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))