452 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,  in b43_dmacontroller_rx_reset()  argument
462 	b43_write32(dev, mmio_base + offset, 0);  in b43_dmacontroller_rx_reset()
466 		value = b43_read32(dev, mmio_base + offset);  in b43_dmacontroller_rx_reset()
491 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,  in b43_dmacontroller_tx_reset()  argument
503 		value = b43_read32(dev, mmio_base + offset);  in b43_dmacontroller_tx_reset()
520 	b43_write32(dev, mmio_base + offset, 0);  in b43_dmacontroller_tx_reset()
524 		value = b43_read32(dev, mmio_base + offset);  in b43_dmacontroller_tx_reset()
769 		b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,  in dmacontroller_cleanup()
777 		b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,  in dmacontroller_cleanup()
816 	u16 mmio_base;  in supported_dma_mask()  local
835 	mmio_base = b43_dmacontroller_base(0, 0);  in supported_dma_mask()
836 	b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);  in supported_dma_mask()
837 	tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);  in supported_dma_mask()
884 	ring->mmio_base = b43_dmacontroller_base(type, controller_index);  in b43_setup_dmaring()
1800 			   u16 mmio_base, bool enable)  in direct_fifo_rx()  argument
1805 		ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);  in direct_fifo_rx()
1809 		b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);  in direct_fifo_rx()
1811 		ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);  in direct_fifo_rx()
1815 		b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);  in direct_fifo_rx()
1825 	u16 mmio_base;  in b43_dma_direct_fifo_rx()  local
1829 	mmio_base = b43_dmacontroller_base(type, engine_index);  in b43_dma_direct_fifo_rx()
1830 	direct_fifo_rx(dev, type, mmio_base, enable);  in b43_dma_direct_fifo_rx()