529 #define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)  macro
531 #define S(a, v) W(a, R(a) | v)
533 #define C(a, v) W(a, R(a) & ~v)
537 	W(RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST);  in wil_halt_cpu()
538 	W(RGF_USER_MAC_CPU_0,  BIT_USER_MAC_CPU_MAN_RST);  in wil_halt_cpu()
544 	W(RGF_USER_USER_CPU_0, 1);  in wil_release_cpu()
562 	W(RGF_USER_BL + offsetof(struct RGF_BL, ready), 0);  in wil_target_reset()
580 	W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);  in wil_target_reset()
581 	W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);  in wil_target_reset()
583 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);  in wil_target_reset()
584 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);  in wil_target_reset()
585 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0);  in wil_target_reset()
586 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FE00);  in wil_target_reset()
588 	W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);  in wil_target_reset()
589 	W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);  in wil_target_reset()
591 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);  in wil_target_reset()
592 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);  in wil_target_reset()
593 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);  in wil_target_reset()
594 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);  in wil_target_reset()
596 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);  in wil_target_reset()
597 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000); /* reset A2 PCIE AHB */  in wil_target_reset()
599 	W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);  in wil_target_reset()
743 		W(RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);  in wil_reset()
768 #undef W