167 #define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)  macro
180 	W(RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
181 	W(RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);  in wil_configure_interrupt_moderation()
185 	W(RGF_DMA_ITR_TX_CNT_CTL,  in wil_configure_interrupt_moderation()
189 	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
190 	W(RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);  in wil_configure_interrupt_moderation()
194 	W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |  in wil_configure_interrupt_moderation()
198 	W(RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
199 	W(RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);  in wil_configure_interrupt_moderation()
203 	W(RGF_DMA_ITR_RX_CNT_CTL,  in wil_configure_interrupt_moderation()
207 	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);  in wil_configure_interrupt_moderation()
208 	W(RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);  in wil_configure_interrupt_moderation()
212 	W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |  in wil_configure_interrupt_moderation()
216 #undef W