Lines Matching refs:HOSTADDR

80 		  HOSTADDR(RGF_DMA_EP_TX_ICR) +  in wil6210_mask_irq_tx()
87 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_mask_irq_rx()
94 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_mask_irq_misc()
103 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW)); in wil6210_mask_irq_pseudo()
111 HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_unmask_irq_tx()
118 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_unmask_irq_rx()
125 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_unmask_irq_misc()
136 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW)); in wil6210_unmask_irq_pseudo()
153 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil_unmask_irq()
155 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil_unmask_irq()
157 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil_unmask_irq()
167 #define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
222 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_irq_rx()
283 HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_irq_tx()
349 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_irq_misc()
450 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_debug_irq_mask()
453 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_debug_irq_mask()
456 HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_debug_irq_mask()
459 HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_debug_irq_mask()
462 HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_debug_irq_mask()
465 HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_debug_irq_mask()
468 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_debug_irq_mask()
471 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_debug_irq_mask()
474 HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_debug_irq_mask()
495 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE)); in wil6210_hardirq()
590 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
592 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
594 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()