205 	struct base_eep_header *pBase = &eep->baseEepHeader;  in ath9k_hw_def_dump_eeprom()  local
219 	PR_EEP("Major Version", pBase->version >> 12);  in ath9k_hw_def_dump_eeprom()
220 	PR_EEP("Minor Version", pBase->version & 0xFFF);  in ath9k_hw_def_dump_eeprom()
221 	PR_EEP("Checksum", pBase->checksum);  in ath9k_hw_def_dump_eeprom()
222 	PR_EEP("Length", pBase->length);  in ath9k_hw_def_dump_eeprom()
223 	PR_EEP("RegDomain1", pBase->regDmn[0]);  in ath9k_hw_def_dump_eeprom()
224 	PR_EEP("RegDomain2", pBase->regDmn[1]);  in ath9k_hw_def_dump_eeprom()
225 	PR_EEP("TX Mask", pBase->txMask);  in ath9k_hw_def_dump_eeprom()
226 	PR_EEP("RX Mask", pBase->rxMask);  in ath9k_hw_def_dump_eeprom()
227 	PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));  in ath9k_hw_def_dump_eeprom()
228 	PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));  in ath9k_hw_def_dump_eeprom()
229 	PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
231 	PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
233 	PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
235 	PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &  in ath9k_hw_def_dump_eeprom()
237 	PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));  in ath9k_hw_def_dump_eeprom()
238 	PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);  in ath9k_hw_def_dump_eeprom()
239 	PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);  in ath9k_hw_def_dump_eeprom()
240 	PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);  in ath9k_hw_def_dump_eeprom()
241 	PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);  in ath9k_hw_def_dump_eeprom()
244 			 pBase->macAddr);  in ath9k_hw_def_dump_eeprom()
384 	struct base_eep_header *pBase = &eep->baseEepHeader;  in ath9k_hw_def_get_eeprom()  local
393 		return get_unaligned_be16(pBase->macAddr);  in ath9k_hw_def_get_eeprom()
395 		return get_unaligned_be16(pBase->macAddr + 2);  in ath9k_hw_def_get_eeprom()
397 		return get_unaligned_be16(pBase->macAddr + 4);  in ath9k_hw_def_get_eeprom()
399 		return pBase->regDmn[0];  in ath9k_hw_def_get_eeprom()
401 		return pBase->deviceCap;  in ath9k_hw_def_get_eeprom()
403 		return pBase->opCapFlags;  in ath9k_hw_def_get_eeprom()
405 		return pBase->rfSilent;  in ath9k_hw_def_get_eeprom()
417 		return pBase->txMask;  in ath9k_hw_def_get_eeprom()
419 		return pBase->rxMask;  in ath9k_hw_def_get_eeprom()
421 		return pBase->fastClk5g;  in ath9k_hw_def_get_eeprom()
423 		return pBase->rxGainType;  in ath9k_hw_def_get_eeprom()
425 		return pBase->txGainType;  in ath9k_hw_def_get_eeprom()
428 			return pBase->openLoopPwrCntl ? true : false;  in ath9k_hw_def_get_eeprom()
433 			return pBase->rcChainMask;  in ath9k_hw_def_get_eeprom()
438 			return pBase->dacHiPwrMode_5G;  in ath9k_hw_def_get_eeprom()
443 			return pBase->frac_n_5g;  in ath9k_hw_def_get_eeprom()
448 			return pBase->pwr_table_offset;  in ath9k_hw_def_get_eeprom()