839 	u32 regVal;  in ath9k_hw_4k_set_board_values()  local
854 		regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ath9k_hw_4k_set_board_values()
855 		regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));  in ath9k_hw_4k_set_board_values()
857 		regVal |= SM(ant_div_control1,  in ath9k_hw_4k_set_board_values()
859 		regVal |= SM(ant_div_control2,  in ath9k_hw_4k_set_board_values()
861 		regVal |= SM((ant_div_control2 >> 2),  in ath9k_hw_4k_set_board_values()
863 		regVal |= SM((ant_div_control1 >> 1),  in ath9k_hw_4k_set_board_values()
865 		regVal |= SM((ant_div_control1 >> 2),  in ath9k_hw_4k_set_board_values()
869 		REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);  in ath9k_hw_4k_set_board_values()
870 		regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ath9k_hw_4k_set_board_values()
871 		regVal = REG_READ(ah, AR_PHY_CCK_DETECT);  in ath9k_hw_4k_set_board_values()
872 		regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);  in ath9k_hw_4k_set_board_values()
873 		regVal |= SM((ant_div_control1 >> 3),  in ath9k_hw_4k_set_board_values()
876 		REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);  in ath9k_hw_4k_set_board_values()
877 		regVal = REG_READ(ah, AR_PHY_CCK_DETECT);  in ath9k_hw_4k_set_board_values()
884 			regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ath9k_hw_4k_set_board_values()
885 			regVal &= (~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |  in ath9k_hw_4k_set_board_values()
888 			regVal |= (ATH_ANT_DIV_COMB_LNA1 <<  in ath9k_hw_4k_set_board_values()
890 			regVal |= (ATH_ANT_DIV_COMB_LNA2 <<  in ath9k_hw_4k_set_board_values()
892 			regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS));  in ath9k_hw_4k_set_board_values()
893 			regVal |= (0 << AR_PHY_9285_FAST_DIV_BIAS_S);  in ath9k_hw_4k_set_board_values()
894 			REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);  in ath9k_hw_4k_set_board_values()