355 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_set_4k_power_cal_table()  local
366 	xpdMask = pEepData->modalHeader.xpdGain;  in ath9k_hw_set_4k_power_cal_table()
368 	if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=  in ath9k_hw_set_4k_power_cal_table()
371 			pEepData->modalHeader.pdGainOverlap;  in ath9k_hw_set_4k_power_cal_table()
377 	pCalBChans = pEepData->calFreqPier2G;  in ath9k_hw_set_4k_power_cal_table()
405 		if (pEepData->baseEepHeader.txMask & (1 << i)) {  in ath9k_hw_set_4k_power_cal_table()
406 			pRawDataset = pEepData->calPierData2G[i];  in ath9k_hw_set_4k_power_cal_table()
465 	 pEepData->ctlIndex[i])						\  in ath9k_hw_set_4k_power_per_rate_table()
467 	    ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))  in ath9k_hw_set_4k_power_per_rate_table()
478 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_set_4k_power_per_rate_table()  local
501 			pEepData->calTargetPowerCck,  in ath9k_hw_set_4k_power_per_rate_table()
505 			pEepData->calTargetPower2G,  in ath9k_hw_set_4k_power_per_rate_table()
509 			pEepData->calTargetPower2GHT20,  in ath9k_hw_set_4k_power_per_rate_table()
516 				pEepData->calTargetPower2GHT40,  in ath9k_hw_set_4k_power_per_rate_table()
520 				pEepData->calTargetPowerCck,  in ath9k_hw_set_4k_power_per_rate_table()
524 				pEepData->calTargetPower2G,  in ath9k_hw_set_4k_power_per_rate_table()
543 			     pEepData->ctlIndex[i]; i++) {  in ath9k_hw_set_4k_power_per_rate_table()
546 				rep = &(pEepData->ctlData[i]);  in ath9k_hw_set_4k_power_per_rate_table()
653 	struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;  in ath9k_hw_4k_set_txpower()  local
654 	struct modal_eep_4k_header *pModal = &pEepData->modalHeader;  in ath9k_hw_4k_set_txpower()
661 	if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=  in ath9k_hw_4k_set_txpower()