Lines Matching refs:u32

23 static const u32 ar9300_2p2_radio_postamble[][5] = {
36 static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
142 static const u32 ar9300Modes_fast_clock_2p2[][3] = {
155 static const u32 ar9300_2p2_radio_core[][2] = {
299 static const u32 ar9300_2p2_mac_postamble[][5] = {
311 static const u32 ar9300_2p2_soc_postamble[][5] = {
316 static const u32 ar9300_2p2_baseband_postamble[][5] = {
372 static const u32 ar9300_2p2_baseband_core[][2] = {
535 static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
641 static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
747 static const u32 ar9300Modes_mixed_ob_db_tx_gain_table_2p2[][5] = {
853 static const u32 ar9300Modes_type5_tx_gain_table_2p2[][5] = {
927 static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
1187 static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
1293 static const u32 ar9300_2p2_mac_core[][2] = {
1450 static const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2] = {
1710 static const u32 ar9300_2p2_soc_preamble[][2] = {
1720 static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
1727 static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
1734 static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
1741 static const u32 ar9300_2p2_baseband_core_txfir_coeff_japan_2484[][2] = {
1748 static const u32 ar9300_2p2_baseband_postamble_dfs_channel[][3] = {