Lines Matching refs:ar
150 #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) argument
151 #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) argument
297 #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask
306 #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
307 #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
311 #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
320 #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
321 #define CE0_BASE_ADDRESS ar->regs->ce0_base_address
322 #define CE1_BASE_ADDRESS ar->regs->ce1_base_address
323 #define CE2_BASE_ADDRESS ar->regs->ce2_base_address
324 #define CE3_BASE_ADDRESS ar->regs->ce3_base_address
325 #define CE4_BASE_ADDRESS ar->regs->ce4_base_address
326 #define CE5_BASE_ADDRESS ar->regs->ce5_base_address
327 #define CE6_BASE_ADDRESS ar->regs->ce6_base_address
328 #define CE7_BASE_ADDRESS ar->regs->ce7_base_address
335 #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
336 #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
350 #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
406 #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address