Lines Matching refs:ath10k_pci_read32

72 	return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);  in ath10k_ce_dest_ring_write_index_get()
85 	return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);  in ath10k_ce_src_ring_write_index_get()
91 	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);  in ath10k_ce_src_ring_read_index_get()
112 	u32 ctrl1_addr = ath10k_pci_read32((ar),  in ath10k_ce_src_ring_dmax_set()
124 	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);  in ath10k_ce_src_ring_byte_swap_set()
135 	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);  in ath10k_ce_dest_ring_byte_swap_set()
145 	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);  in ath10k_ce_dest_ring_read_index_get()
166 	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);  in ath10k_ce_src_ring_highmark_set()
177 	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);  in ath10k_ce_src_ring_lowmark_set()
188 	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);  in ath10k_ce_dest_ring_highmark_set()
199 	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);  in ath10k_ce_dest_ring_lowmark_set()
209 	u32 host_ie_addr = ath10k_pci_read32(ar,  in ath10k_ce_copy_complete_inter_enable()
219 	u32 host_ie_addr = ath10k_pci_read32(ar,  in ath10k_ce_copy_complete_intr_disable()
229 	u32 host_ie_addr = ath10k_pci_read32(ar,  in ath10k_ce_watermark_intr_disable()
239 	u32 misc_ie_addr = ath10k_pci_read32(ar,  in ath10k_ce_error_intr_enable()
249 	u32 misc_ie_addr = ath10k_pci_read32(ar,  in ath10k_ce_error_intr_disable()