Lines Matching refs:a1
320 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address
327 movel %d3, (%a1)+ // TX flags + length
328 movel %d1, (%a1)+ // buffer address
333 movel %d3, (%a1)+ // Final TX flags + length
334 movel %d1, (%a1)+ // buffer address
339 movel #0x90000000, (%a1)+ // RX flags + length
340 movel %d1, (%a1)+ // buffer address
344 movel #0xB0000000, (%a1)+ // Final RX flags + length
345 movel %d1, (%a1)+ // buffer address
348 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address
355 movew %d1, SCC_TBASE(%a1) // D1 = offset of first TxBD
357 movew %d1, SCC_RBASE(%a1) // D1 = offset of first RxBD
358 moveb #0x8, SCC_RFCR(%a1) // Intel mode, 1000
359 moveb #0x8, SCC_TFCR(%a1)
365 movel #0xF0B8, SCC_C_MASK(%a1)
366 movel #0xFFFF, SCC_C_PRES(%a1)
367 movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
375 movel #0xDEBB20E3, SCC_C_MASK(%a1)
376 movel #0xFFFFFFFF, SCC_C_PRES(%a1)
377 movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
385 movel #0xF0B8, SCC_C_MASK(%a1)
386 clrl SCC_C_PRES(%a1)
387 movew #HDLC_MAX_MRU + 2, SCC_MFLR(%a1) // 2 bytes for CRC
395 movel #0xDEBB20E3, SCC_C_MASK(%a1)
396 clrl SCC_C_PRES(%a1)
397 movew #HDLC_MAX_MRU + 4, SCC_MFLR(%a1) // 4 bytes for CRC
403 movel #0xF0B8, SCC_C_MASK(%a1)
404 movel #0xFFFF, SCC_C_PRES(%a1)
405 movew #HDLC_MAX_MRU, SCC_MFLR(%a1) // 0 bytes for CRC
418 movew #BUFFER_LENGTH, SCC_MRBLR(%a1)
466 movel 4(%d1), %a1 // A1 = dest address
469 memcpy_from_pci %a0, %a1, %d2
521 movel 4(%d2), %a1
522 tstl %a1
524 memcpy_to_pci %a0, %a1, %d3
691 movel %a1, -(%sp)
752 movel ch_status_addr(%d0), %a1
753 cmpl STATUS_CABLE(%a1), %d1 // check for change
755 movel %d1, STATUS_CABLE(%a1) // update status
764 movel (%sp)+, %a1