78 	u8 __iomem *plx;	/* PLX PCI9060 virtual base address */  member
254         while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {  in wanxl_intr()
256 		writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);  in wanxl_intr()
302 	       port->card->plx + PLX_DOORBELL_TO_CARD);  in wanxl_xmit()
397 	u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;  in wanxl_open()
439 	       port->card->plx + PLX_DOORBELL_TO_CARD);  in wanxl_close()
485 	writel(cmd, card->plx + PLX_MAILBOX_1);  in wanxl_puts_command()
487 		if (readl(card->plx + PLX_MAILBOX_1) == 0)  in wanxl_puts_command()
500 	u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;  in wanxl_reset()
502 	writel(0x80, card->plx + PLX_MAILBOX_0);  in wanxl_reset()
503 	writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);  in wanxl_reset()
504 	readl(card->plx + PLX_CONTROL); /* wait for posted write */  in wanxl_reset()
506 	writel(old_value, card->plx + PLX_CONTROL);  in wanxl_reset()
507 	readl(card->plx + PLX_CONTROL); /* wait for posted write */  in wanxl_reset()
536 	if (card->plx)  in wanxl_pci_remove_one()
537 		iounmap(card->plx);  in wanxl_pci_remove_one()
642 	card->plx = ioremap_nocache(plx_phy, 0x70);  in wanxl_pci_init_one()
643 	if (!card->plx) {  in wanxl_pci_init_one()
654 	while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {  in wanxl_pci_init_one()
678 	ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;  in wanxl_pci_init_one()
729 	writel(0, card->plx + PLX_MAILBOX_5);  in wanxl_pci_init_one()
740 		if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)  in wanxl_pci_init_one()