404 static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,  in scc_writel()  function
629 	scc_writel(0x00050000, dpriv, dev, CCR2);
857 	scc_writel(0x00000000, dpriv, dev, CCR0);  in dscc4_init_registers()
859 	scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);  in dscc4_init_registers()
867 	scc_writel(0x02408000, dpriv, dev, CCR1);  in dscc4_init_registers()
870 	scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);  in dscc4_init_registers()
1073 		scc_writel(EventsMask, dpriv, dev, IMR);  in dscc4_open()
1097 	scc_writel(EventsMask, dpriv, dev, IMR);  in dscc4_open()
1100 	scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);  in dscc4_open()
1133 	scc_writel(0xffffffff, dpriv, dev, IMR);  in dscc4_open()
1193 	scc_writel(0xffffffff, dpriv, dev, IMR);  in dscc4_close()
1303 	scc_writel(brr, dpriv, dev, BRR);  in dscc4_set_clock()
1390 	scc_writel(state, dpriv, dev, CCR0);  in dscc4_clock_setting()
1431 	scc_writel(state, dpriv, dev, CCR1);  in dscc4_loopback_setting()
1672 				scc_writel(0x08050008, dpriv, dev, CCR2);  in dscc4_tx_irq()
1816 			scc_writel(RxSccRes, dpriv, dev, CMDR);  in dscc4_rx_irq()