97 #define port_to_card(port)	   (port)  argument
98 #define log_node(port)		   (0)  argument
99 #define phy_node(port)		   (0)  argument
103 #define get_port(card, port)	   (card)  argument
104 static void sca_msci_intr(port_t *port);
122 static inline void set_carrier(port_t *port)  in set_carrier()  argument
124 	if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))  in set_carrier()
125 		netif_carrier_on(port_to_dev(port));  in set_carrier()
127 		netif_carrier_off(port_to_dev(port));  in set_carrier()
131 static void sca_msci_intr(port_t *port)  in sca_msci_intr()  argument
133 	u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */  in sca_msci_intr()
136 	sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);  in sca_msci_intr()
140 		port_to_dev(port)->stats.tx_errors++;  in sca_msci_intr()
141 		port_to_dev(port)->stats.tx_fifo_errors++;  in sca_msci_intr()
144 	stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */  in sca_msci_intr()
146 	sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);  in sca_msci_intr()
149 		set_carrier(port);  in sca_msci_intr()
153 static void c101_set_iface(port_t *port)  in c101_set_iface()  argument
155 	u8 rxs = port->rxs & CLK_BRG_MASK;  in c101_set_iface()
156 	u8 txs = port->txs & CLK_BRG_MASK;  in c101_set_iface()
158 	switch(port->settings.clock_type) {  in c101_set_iface()
179 	port->rxs = rxs;  in c101_set_iface()
180 	port->txs = txs;  in c101_set_iface()
181 	sca_out(rxs, MSCI1_OFFSET + RXS, port);  in c101_set_iface()
182 	sca_out(txs, MSCI1_OFFSET + TXS, port);  in c101_set_iface()
183 	sca_set_port(port);  in c101_set_iface()
189 	port_t *port = dev_to_port(dev);  in c101_open()  local
196 	writeb(1, port->win0base + C101_DTR);  in c101_open()
197 	sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */  in c101_open()
200 	sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);  in c101_open()
201 	sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);  in c101_open()
203 	set_carrier(port);  in c101_open()
206 	sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);  in c101_open()
207 	sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);  in c101_open()
208 	sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */  in c101_open()
209 	c101_set_iface(port);  in c101_open()
216 	port_t *port = dev_to_port(dev);  in c101_close()  local
219 	writeb(0, port->win0base + C101_DTR);  in c101_close()
220 	sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);  in c101_close()
231 	port_t *port = dev_to_port(dev);  in c101_ioctl()  local
237 		       sca_in(MSCI1_OFFSET + ST0, port),  in c101_ioctl()
238 		       sca_in(MSCI1_OFFSET + ST1, port),  in c101_ioctl()
239 		       sca_in(MSCI1_OFFSET + ST2, port),  in c101_ioctl()
240 		       sca_in(MSCI1_OFFSET + ST3, port));  in c101_ioctl()
254 		if (copy_to_user(line, &port->settings, size))  in c101_ioctl()
274 		memcpy(&port->settings, &new_line, size); /* Update settings */  in c101_ioctl()
275 		c101_set_iface(port);  in c101_ioctl()