Lines Matching refs:phydev
397 struct phy_device *phydev; member
445 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev) in amd_xgbe_an_enable_kr_training() argument
449 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in amd_xgbe_an_enable_kr_training()
454 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); in amd_xgbe_an_enable_kr_training()
459 static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev) in amd_xgbe_an_disable_kr_training() argument
463 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in amd_xgbe_an_disable_kr_training()
468 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret); in amd_xgbe_an_disable_kr_training()
473 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev) in amd_xgbe_phy_pcs_power_cycle() argument
477 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_pcs_power_cycle()
482 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_pcs_power_cycle()
487 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_pcs_power_cycle()
492 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev) in amd_xgbe_phy_serdes_start_ratechange() argument
494 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_serdes_start_ratechange()
500 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev) in amd_xgbe_phy_serdes_complete_ratechange() argument
502 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_serdes_complete_ratechange()
520 netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n", in amd_xgbe_phy_serdes_complete_ratechange()
529 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev) in amd_xgbe_phy_xgmii_mode() argument
531 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_xgmii_mode()
535 ret = amd_xgbe_an_enable_kr_training(phydev); in amd_xgbe_phy_xgmii_mode()
540 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); in amd_xgbe_phy_xgmii_mode()
546 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); in amd_xgbe_phy_xgmii_mode()
548 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_xgmii_mode()
554 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_xgmii_mode()
556 ret = amd_xgbe_phy_pcs_power_cycle(phydev); in amd_xgbe_phy_xgmii_mode()
561 amd_xgbe_phy_serdes_start_ratechange(phydev); in amd_xgbe_phy_xgmii_mode()
580 amd_xgbe_phy_serdes_complete_ratechange(phydev); in amd_xgbe_phy_xgmii_mode()
585 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev) in amd_xgbe_phy_gmii_2500_mode() argument
587 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_gmii_2500_mode()
591 ret = amd_xgbe_an_disable_kr_training(phydev); in amd_xgbe_phy_gmii_2500_mode()
596 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); in amd_xgbe_phy_gmii_2500_mode()
602 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); in amd_xgbe_phy_gmii_2500_mode()
604 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_gmii_2500_mode()
610 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_gmii_2500_mode()
612 ret = amd_xgbe_phy_pcs_power_cycle(phydev); in amd_xgbe_phy_gmii_2500_mode()
617 amd_xgbe_phy_serdes_start_ratechange(phydev); in amd_xgbe_phy_gmii_2500_mode()
636 amd_xgbe_phy_serdes_complete_ratechange(phydev); in amd_xgbe_phy_gmii_2500_mode()
641 static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev) in amd_xgbe_phy_gmii_mode() argument
643 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_gmii_mode()
647 ret = amd_xgbe_an_disable_kr_training(phydev); in amd_xgbe_phy_gmii_mode()
652 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); in amd_xgbe_phy_gmii_mode()
658 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret); in amd_xgbe_phy_gmii_mode()
660 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_gmii_mode()
666 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_gmii_mode()
668 ret = amd_xgbe_phy_pcs_power_cycle(phydev); in amd_xgbe_phy_gmii_mode()
673 amd_xgbe_phy_serdes_start_ratechange(phydev); in amd_xgbe_phy_gmii_mode()
692 amd_xgbe_phy_serdes_complete_ratechange(phydev); in amd_xgbe_phy_gmii_mode()
697 static int amd_xgbe_phy_cur_mode(struct phy_device *phydev, in amd_xgbe_phy_cur_mode() argument
702 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2); in amd_xgbe_phy_cur_mode()
714 static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev) in amd_xgbe_phy_in_kr_mode() argument
718 if (amd_xgbe_phy_cur_mode(phydev, &mode)) in amd_xgbe_phy_in_kr_mode()
724 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev) in amd_xgbe_phy_switch_mode() argument
726 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_switch_mode()
730 if (amd_xgbe_phy_in_kr_mode(phydev)) { in amd_xgbe_phy_switch_mode()
732 ret = amd_xgbe_phy_gmii_mode(phydev); in amd_xgbe_phy_switch_mode()
734 ret = amd_xgbe_phy_gmii_2500_mode(phydev); in amd_xgbe_phy_switch_mode()
736 ret = amd_xgbe_phy_xgmii_mode(phydev); in amd_xgbe_phy_switch_mode()
742 static int amd_xgbe_phy_set_mode(struct phy_device *phydev, in amd_xgbe_phy_set_mode() argument
748 ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode); in amd_xgbe_phy_set_mode()
753 ret = amd_xgbe_phy_switch_mode(phydev); in amd_xgbe_phy_set_mode()
758 static bool amd_xgbe_phy_use_xgmii_mode(struct phy_device *phydev) in amd_xgbe_phy_use_xgmii_mode() argument
760 if (phydev->autoneg == AUTONEG_ENABLE) { in amd_xgbe_phy_use_xgmii_mode()
761 if (phydev->advertising & ADVERTISED_10000baseKR_Full) in amd_xgbe_phy_use_xgmii_mode()
764 if (phydev->speed == SPEED_10000) in amd_xgbe_phy_use_xgmii_mode()
771 static bool amd_xgbe_phy_use_gmii_2500_mode(struct phy_device *phydev) in amd_xgbe_phy_use_gmii_2500_mode() argument
773 if (phydev->autoneg == AUTONEG_ENABLE) { in amd_xgbe_phy_use_gmii_2500_mode()
774 if (phydev->advertising & ADVERTISED_2500baseX_Full) in amd_xgbe_phy_use_gmii_2500_mode()
777 if (phydev->speed == SPEED_2500) in amd_xgbe_phy_use_gmii_2500_mode()
784 static bool amd_xgbe_phy_use_gmii_mode(struct phy_device *phydev) in amd_xgbe_phy_use_gmii_mode() argument
786 if (phydev->autoneg == AUTONEG_ENABLE) { in amd_xgbe_phy_use_gmii_mode()
787 if (phydev->advertising & ADVERTISED_1000baseKX_Full) in amd_xgbe_phy_use_gmii_mode()
790 if (phydev->speed == SPEED_1000) in amd_xgbe_phy_use_gmii_mode()
797 static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable, in amd_xgbe_phy_set_an() argument
802 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in amd_xgbe_phy_set_an()
814 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret); in amd_xgbe_phy_set_an()
819 static int amd_xgbe_phy_restart_an(struct phy_device *phydev) in amd_xgbe_phy_restart_an() argument
821 return amd_xgbe_phy_set_an(phydev, true, true); in amd_xgbe_phy_restart_an()
824 static int amd_xgbe_phy_disable_an(struct phy_device *phydev) in amd_xgbe_phy_disable_an() argument
826 return amd_xgbe_phy_set_an(phydev, false, false); in amd_xgbe_phy_disable_an()
829 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev, in amd_xgbe_an_tx_training() argument
832 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_an_tx_training()
838 if (!amd_xgbe_phy_in_kr_mode(phydev)) in amd_xgbe_an_tx_training()
842 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in amd_xgbe_an_tx_training()
846 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2); in amd_xgbe_an_tx_training()
850 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL); in amd_xgbe_an_tx_training()
858 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret); in amd_xgbe_an_tx_training()
861 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL); in amd_xgbe_an_tx_training()
869 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, in amd_xgbe_an_tx_training()
878 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev, in amd_xgbe_an_tx_xnp() argument
888 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0); in amd_xgbe_an_tx_xnp()
889 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0); in amd_xgbe_an_tx_xnp()
890 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg); in amd_xgbe_an_tx_xnp()
895 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev, in amd_xgbe_an_rx_bpa() argument
902 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); in amd_xgbe_an_rx_bpa()
907 link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20; in amd_xgbe_an_rx_bpa()
912 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in amd_xgbe_an_rx_bpa()
916 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in amd_xgbe_an_rx_bpa()
921 amd_xgbe_an_tx_xnp(phydev, state) : in amd_xgbe_an_rx_bpa()
922 amd_xgbe_an_tx_training(phydev, state); in amd_xgbe_an_rx_bpa()
925 static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev, in amd_xgbe_an_rx_xnp() argument
931 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP); in amd_xgbe_an_rx_xnp()
935 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX); in amd_xgbe_an_rx_xnp()
940 amd_xgbe_an_tx_xnp(phydev, state) : in amd_xgbe_an_rx_xnp()
941 amd_xgbe_an_tx_training(phydev, state); in amd_xgbe_an_rx_xnp()
944 static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev) in amd_xgbe_an_page_received() argument
946 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_an_page_received()
965 state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state in amd_xgbe_an_page_received()
970 ret = amd_xgbe_an_rx_bpa(phydev, state); in amd_xgbe_an_page_received()
974 ret = amd_xgbe_an_rx_xnp(phydev, state); in amd_xgbe_an_page_received()
984 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev) in amd_xgbe_an_incompat_link() argument
986 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_an_incompat_link()
990 if (amd_xgbe_phy_in_kr_mode(phydev)) { in amd_xgbe_an_incompat_link()
993 if (!(phydev->advertising & SUPPORTED_1000baseKX_Full) && in amd_xgbe_an_incompat_link()
994 !(phydev->advertising & SUPPORTED_2500baseX_Full)) in amd_xgbe_an_incompat_link()
1002 if (!(phydev->advertising & SUPPORTED_10000baseKR_Full)) in amd_xgbe_an_incompat_link()
1009 ret = amd_xgbe_phy_disable_an(phydev); in amd_xgbe_an_incompat_link()
1013 ret = amd_xgbe_phy_switch_mode(phydev); in amd_xgbe_an_incompat_link()
1017 ret = amd_xgbe_phy_restart_an(phydev); in amd_xgbe_an_incompat_link()
1054 struct phy_device *phydev = priv->phydev; in amd_xgbe_an_state_machine() local
1061 int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT); in amd_xgbe_an_state_machine()
1085 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg); in amd_xgbe_an_state_machine()
1098 priv->an_state = amd_xgbe_an_page_received(phydev); in amd_xgbe_an_state_machine()
1105 priv->an_state = amd_xgbe_an_incompat_link(phydev); in amd_xgbe_an_state_machine()
1110 netdev_dbg(phydev->attached_dev, "%s successful\n", in amd_xgbe_an_state_machine()
1124 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); in amd_xgbe_an_state_machine()
1126 netdev_err(phydev->attached_dev, in amd_xgbe_an_state_machine()
1131 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); in amd_xgbe_an_state_machine()
1154 static int amd_xgbe_an_init(struct phy_device *phydev) in amd_xgbe_an_init() argument
1159 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in amd_xgbe_an_init()
1163 if (phydev->advertising & SUPPORTED_10000baseR_FEC) in amd_xgbe_an_init()
1168 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret); in amd_xgbe_an_init()
1171 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in amd_xgbe_an_init()
1175 if (phydev->advertising & SUPPORTED_10000baseKR_Full) in amd_xgbe_an_init()
1180 if ((phydev->advertising & SUPPORTED_1000baseKX_Full) || in amd_xgbe_an_init()
1181 (phydev->advertising & SUPPORTED_2500baseX_Full)) in amd_xgbe_an_init()
1186 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret); in amd_xgbe_an_init()
1189 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in amd_xgbe_an_init()
1193 if (phydev->advertising & SUPPORTED_Pause) in amd_xgbe_an_init()
1198 if (phydev->advertising & SUPPORTED_Asym_Pause) in amd_xgbe_an_init()
1206 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret); in amd_xgbe_an_init()
1211 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev) in amd_xgbe_phy_soft_reset() argument
1215 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_soft_reset()
1220 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_soft_reset()
1225 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_soft_reset()
1234 ret = amd_xgbe_phy_disable_an(phydev); in amd_xgbe_phy_soft_reset()
1239 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); in amd_xgbe_phy_soft_reset()
1244 static int amd_xgbe_phy_config_init(struct phy_device *phydev) in amd_xgbe_phy_config_init() argument
1246 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_config_init()
1247 struct net_device *netdev = phydev->attached_dev; in amd_xgbe_phy_config_init()
1277 if (amd_xgbe_phy_use_xgmii_mode(phydev)) in amd_xgbe_phy_config_init()
1278 ret = amd_xgbe_phy_xgmii_mode(phydev); in amd_xgbe_phy_config_init()
1279 else if (amd_xgbe_phy_use_gmii_mode(phydev)) in amd_xgbe_phy_config_init()
1280 ret = amd_xgbe_phy_gmii_mode(phydev); in amd_xgbe_phy_config_init()
1281 else if (amd_xgbe_phy_use_gmii_2500_mode(phydev)) in amd_xgbe_phy_config_init()
1282 ret = amd_xgbe_phy_gmii_2500_mode(phydev); in amd_xgbe_phy_config_init()
1289 ret = amd_xgbe_an_init(phydev); in amd_xgbe_phy_config_init()
1294 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07); in amd_xgbe_phy_config_init()
1299 static int amd_xgbe_phy_setup_forced(struct phy_device *phydev) in amd_xgbe_phy_setup_forced() argument
1304 ret = amd_xgbe_phy_disable_an(phydev); in amd_xgbe_phy_setup_forced()
1309 switch (phydev->speed) { in amd_xgbe_phy_setup_forced()
1311 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); in amd_xgbe_phy_setup_forced()
1316 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); in amd_xgbe_phy_setup_forced()
1327 if (phydev->duplex != DUPLEX_FULL) in amd_xgbe_phy_setup_forced()
1330 phydev->pause = 0; in amd_xgbe_phy_setup_forced()
1331 phydev->asym_pause = 0; in amd_xgbe_phy_setup_forced()
1336 static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev) in __amd_xgbe_phy_config_aneg() argument
1338 struct amd_xgbe_phy_priv *priv = phydev->priv; in __amd_xgbe_phy_config_aneg()
1339 u32 mmd_mask = phydev->c45_ids.devices_in_package; in __amd_xgbe_phy_config_aneg()
1342 if (phydev->autoneg != AUTONEG_ENABLE) in __amd_xgbe_phy_config_aneg()
1343 return amd_xgbe_phy_setup_forced(phydev); in __amd_xgbe_phy_config_aneg()
1353 if (phydev->advertising & SUPPORTED_10000baseKR_Full) in __amd_xgbe_phy_config_aneg()
1354 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); in __amd_xgbe_phy_config_aneg()
1355 else if ((phydev->advertising & SUPPORTED_1000baseKX_Full) || in __amd_xgbe_phy_config_aneg()
1356 (phydev->advertising & SUPPORTED_2500baseX_Full)) in __amd_xgbe_phy_config_aneg()
1357 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); in __amd_xgbe_phy_config_aneg()
1366 ret = amd_xgbe_phy_disable_an(phydev); in __amd_xgbe_phy_config_aneg()
1371 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0); in __amd_xgbe_phy_config_aneg()
1382 ret = amd_xgbe_an_init(phydev); in __amd_xgbe_phy_config_aneg()
1387 return amd_xgbe_phy_restart_an(phydev); in __amd_xgbe_phy_config_aneg()
1390 static int amd_xgbe_phy_config_aneg(struct phy_device *phydev) in amd_xgbe_phy_config_aneg() argument
1392 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_config_aneg()
1397 ret = __amd_xgbe_phy_config_aneg(phydev); in amd_xgbe_phy_config_aneg()
1404 static int amd_xgbe_phy_aneg_done(struct phy_device *phydev) in amd_xgbe_phy_aneg_done() argument
1406 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_aneg_done()
1411 static int amd_xgbe_phy_update_link(struct phy_device *phydev) in amd_xgbe_phy_update_link() argument
1413 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_update_link()
1418 phydev->link = 1; in amd_xgbe_phy_update_link()
1425 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); in amd_xgbe_phy_update_link()
1429 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1); in amd_xgbe_phy_update_link()
1433 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0; in amd_xgbe_phy_update_link()
1438 static int amd_xgbe_phy_read_status(struct phy_device *phydev) in amd_xgbe_phy_read_status() argument
1440 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_read_status()
1441 u32 mmd_mask = phydev->c45_ids.devices_in_package; in amd_xgbe_phy_read_status()
1444 ret = amd_xgbe_phy_update_link(phydev); in amd_xgbe_phy_read_status()
1448 if ((phydev->autoneg == AUTONEG_ENABLE) && in amd_xgbe_phy_read_status()
1453 if (!amd_xgbe_phy_aneg_done(phydev)) in amd_xgbe_phy_read_status()
1457 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in amd_xgbe_phy_read_status()
1460 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in amd_xgbe_phy_read_status()
1465 phydev->pause = (ad_ret & 0x400) ? 1 : 0; in amd_xgbe_phy_read_status()
1466 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0; in amd_xgbe_phy_read_status()
1469 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, in amd_xgbe_phy_read_status()
1473 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1); in amd_xgbe_phy_read_status()
1479 phydev->speed = SPEED_10000; in amd_xgbe_phy_read_status()
1480 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR); in amd_xgbe_phy_read_status()
1486 phydev->speed = SPEED_1000; in amd_xgbe_phy_read_status()
1490 phydev->speed = SPEED_2500; in amd_xgbe_phy_read_status()
1494 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX); in amd_xgbe_phy_read_status()
1499 phydev->duplex = DUPLEX_FULL; in amd_xgbe_phy_read_status()
1501 if (amd_xgbe_phy_in_kr_mode(phydev)) { in amd_xgbe_phy_read_status()
1502 phydev->speed = SPEED_10000; in amd_xgbe_phy_read_status()
1506 phydev->speed = SPEED_1000; in amd_xgbe_phy_read_status()
1510 phydev->speed = SPEED_2500; in amd_xgbe_phy_read_status()
1514 phydev->duplex = DUPLEX_FULL; in amd_xgbe_phy_read_status()
1515 phydev->pause = 0; in amd_xgbe_phy_read_status()
1516 phydev->asym_pause = 0; in amd_xgbe_phy_read_status()
1522 static int amd_xgbe_phy_suspend(struct phy_device *phydev) in amd_xgbe_phy_suspend() argument
1524 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_suspend()
1527 mutex_lock(&phydev->lock); in amd_xgbe_phy_suspend()
1529 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); in amd_xgbe_phy_suspend()
1536 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret); in amd_xgbe_phy_suspend()
1541 mutex_unlock(&phydev->lock); in amd_xgbe_phy_suspend()
1546 static int amd_xgbe_phy_resume(struct phy_device *phydev) in amd_xgbe_phy_resume() argument
1548 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_resume()
1550 mutex_lock(&phydev->lock); in amd_xgbe_phy_resume()
1553 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl); in amd_xgbe_phy_resume()
1555 mutex_unlock(&phydev->lock); in amd_xgbe_phy_resume()
1576 static int amd_xgbe_phy_probe(struct phy_device *phydev) in amd_xgbe_phy_probe() argument
1584 if (!phydev->bus || !phydev->bus->parent) in amd_xgbe_phy_probe()
1587 dev = phydev->bus->parent; in amd_xgbe_phy_probe()
1596 priv->phydev = phydev; in amd_xgbe_phy_probe()
1785 phydev->supported = SUPPORTED_Autoneg; in amd_xgbe_phy_probe()
1786 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; in amd_xgbe_phy_probe()
1787 phydev->supported |= SUPPORTED_Backplane; in amd_xgbe_phy_probe()
1788 phydev->supported |= SUPPORTED_10000baseKR_Full; in amd_xgbe_phy_probe()
1791 phydev->supported |= SUPPORTED_1000baseKX_Full; in amd_xgbe_phy_probe()
1794 phydev->supported |= SUPPORTED_2500baseX_Full; in amd_xgbe_phy_probe()
1798 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY); in amd_xgbe_phy_probe()
1803 phydev->supported |= SUPPORTED_10000baseR_FEC; in amd_xgbe_phy_probe()
1805 phydev->advertising = phydev->supported; in amd_xgbe_phy_probe()
1807 phydev->priv = priv; in amd_xgbe_phy_probe()
1839 static void amd_xgbe_phy_remove(struct phy_device *phydev) in amd_xgbe_phy_remove() argument
1841 struct amd_xgbe_phy_priv *priv = phydev->priv; in amd_xgbe_phy_remove()
1867 static int amd_xgbe_match_phy_device(struct phy_device *phydev) in amd_xgbe_match_phy_device() argument
1869 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID; in amd_xgbe_match_phy_device()