160 #define SIR1_SPEED			0x0000  macro
497 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);  in amd_xgbe_phy_serdes_start_ratechange()
507 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);  in amd_xgbe_phy_serdes_complete_ratechange()
563 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);  in amd_xgbe_phy_xgmii_mode()
564 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);  in amd_xgbe_phy_xgmii_mode()
565 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);  in amd_xgbe_phy_xgmii_mode()
567 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,  in amd_xgbe_phy_xgmii_mode()
569 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,  in amd_xgbe_phy_xgmii_mode()
619 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);  in amd_xgbe_phy_gmii_2500_mode()
620 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);  in amd_xgbe_phy_gmii_2500_mode()
621 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);  in amd_xgbe_phy_gmii_2500_mode()
623 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,  in amd_xgbe_phy_gmii_2500_mode()
625 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,  in amd_xgbe_phy_gmii_2500_mode()
675 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);  in amd_xgbe_phy_gmii_mode()
676 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);  in amd_xgbe_phy_gmii_mode()
677 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);  in amd_xgbe_phy_gmii_mode()
679 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, CDR_RATE,  in amd_xgbe_phy_gmii_mode()
681 	XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP,  in amd_xgbe_phy_gmii_mode()