802 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);  in amd_xgbe_phy_set_an()
814 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);  in amd_xgbe_phy_set_an()
842 	ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);  in amd_xgbe_an_tx_training()
846 	lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);  in amd_xgbe_an_tx_training()
888 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);  in amd_xgbe_an_tx_xnp()
889 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);  in amd_xgbe_an_tx_xnp()
890 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);  in amd_xgbe_an_tx_xnp()
902 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);  in amd_xgbe_an_rx_bpa()
912 	ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);  in amd_xgbe_an_rx_bpa()
916 	lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);  in amd_xgbe_an_rx_bpa()
931 	ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP);  in amd_xgbe_an_rx_xnp()
935 	lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX);  in amd_xgbe_an_rx_xnp()
1061 	int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);  in amd_xgbe_an_state_machine()
1085 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg);  in amd_xgbe_an_state_machine()
1124 		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);  in amd_xgbe_an_state_machine()
1131 		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);  in amd_xgbe_an_state_machine()
1159 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);  in amd_xgbe_an_init()
1168 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);  in amd_xgbe_an_init()
1171 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);  in amd_xgbe_an_init()
1186 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);  in amd_xgbe_an_init()
1189 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);  in amd_xgbe_an_init()
1206 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);  in amd_xgbe_an_init()
1239 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);  in amd_xgbe_phy_soft_reset()
1294 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);  in amd_xgbe_phy_config_init()
1371 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);  in __amd_xgbe_phy_config_aneg()
1457 		ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);  in amd_xgbe_phy_read_status()
1460 		lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);  in amd_xgbe_phy_read_status()
1469 		ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,  in amd_xgbe_phy_read_status()
1473 		lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);  in amd_xgbe_phy_read_status()